參數(shù)資料
型號： QL3040-0PB456I
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： 40000 usable PLD gate pASIC 3 FPGA combining High performance and high density
中文描述： FPGA, 1008 CLBS, 40000 GATES, 225 MHz, PBGA456
封裝： 35 X 35 MM, 2.33 MM HIEGHT, 1.27 MM PITCH, PLASTIC, MS-034BAR-2, BGA-456
文件頁數(shù)： 45/49頁
文件大小： 885K
代理商： QL3040-0PB456I
2005 QuickLogic Corporation
www.quicklogic.com
pASIC 3 FPGA Family Data Sheet Rev. D
5
Figure 2: Loads used for t
PXZ
Table 5: Clock Cells
Symbol
Parameter
Propagation Delays (ns) Loads per Half Column a
a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven
by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to eight loads
per half column. The global clock has up to 11 loads per half column.
1
2
3
4
8
10
11
t
ACK
Array Clock Delay
1.2
1.3
1.5
1.6
1.7
t
GCKP
Global Clock Pin Delay
0.7
t
GCKB
Global Clock Buffer Delay
0.8
0.9
1.1
1.2
1.3
Table 6: Input-Only I/O Cells
Symbol
Parameter
Propagation Delays (ns) Fanout a
a. Stated timing for worst case Propagation Delay over process variation at V
CC = 3.3 V and TA = 25°C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage, and temperature settings as specified in
1
2
3
4
8
10
tI/O
Input Delay (bidirectional pad)
1.3
1.6
1.8
2.1
3.1
3.6
tISU
Input Register Set-Up Time
3.1
tIH
Input Register Hold Time
0.0
tlOCLK
Input Register Clock To Q
0.7
1.0
1.2
1.5
2.5
3.0
tlORST
Input Register Reset Delay
0.6
0.9
1.1
1.4
2.4
2.9
tlESU
Input Register clock Enable Set-Up Time
2.3
tlEH
Input Register Clock Enable Hold Time
0.0
Table 7: Output-Only I/O Cells
Symbol
Parameter
Propagation Delays (ns) Output Load Capacitance (pF)
30
50
75
100
150
t
OUTLH
Output Delay Low to High
2.1
2.5
3.1
3.6
4.7
t
OUTHL
Output Delay High to Low
2.2
2.6
3.2
3.7
4.8
t
PZH
Output Delay Tri-state to High
1.2
1.7
2.2
2.8
3.9
t
PZL
Output Delay Tri-state to Low
1.6
2.0
2.6
3.1
4.2
t
PHZ
Output Delay High to Tri-State a
a. The loads presented in
Figure 2 are used for t
PXZ:
2.0
-
t
PLZ
Output Delay Low to Tri-State
1.2
-
1Κ
tPHZ
tPLZ
5 pF
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