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參數(shù)資料
| 型號： | QL3025 |
| 廠商： | QuickLogic Corp. |
| 英文描述： | pASIC3 FPGA Combining High Performance and High Density(高性能和高密度相結(jié)合的pASIC3現(xiàn)場可編程門陣列) |
| 中文描述： | pASIC3 FPGA的結(jié)合高性能和高密度（高性能和高密度相結(jié)合的pASIC3現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 239K |
| 代理商： | QL3025 |
24
Preliminary
8-24
Military Plastic pASIC 3 Family
Product Summary
The pASIC 3 FPGA family features up to 60,000
usable PLD gates. pASIC 3 FPGAs are fabricated
on a 0.35mm four-layer metal process using Quick-
Logic’s patented ViaLink technology to provide a
unique combination of high performance, high den-
sity, low cost, and extreme ease-of-use.
The pASIC 3 product family contains 1,584 logic
cells. With a maximum of 316 I/Os, and is available
in 208-PQFP and 84-PLCC packages.
Software support for the complete pASIC 3 family is
available through three basic packages. The turnkey
Quick
Works
package provides the most complete
FPGA software solution from design entry to logic
synthesis, to place and route, to simulation. The
QuickWorks
TM
-Lite and Quick
Tools
TM
packages pro-
vide a solution for designers who use Cadence,
Exemplar, Mentor, Synopsys, Synplicity, Viewlogic,
Veribest, or other third-party tools for design entry,
synthesis, or simulation.
Pinout Diagram 68-Pin CPGA
TABLE 2: 84-pin PLCC
P
RODUCT
S
UMMARY
P
INOUT
D
IAGRAM
84-P
IN
PLCC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL30250PB256C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
| QL3025-0PB256C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL30250PB256I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
| QL3025-0PB256I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL30250PB256M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
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