參數(shù)資料
型號: PXA210
廠商: Intel Corp.
英文描述: Intel-R PXA250 and PXA210 Applications Processors
中文描述: 英特爾- R的PXA250和PXA210應用處理器
文件頁數(shù): 43/46頁
文件大?。?/td> 431K
代理商: PXA210
Electrical, Mechanical, and Thermal Specification
PXA250 and PXA210
Datasheet
43
4.8.1
LCD Module AC Timing
Figure 8 describes the LCD timing parameters. The LCD pin timing specifications are referenced
to the pixel clock (L_PCLK). Values for the parameters are given in Table 21.
4.8.2
SSP Module AC Timing
Figure 9,
SSP AC Timing Definitions
on page 44 describes the SSP timing parameters. The SSP
pin timing specifications are referenced to SCLK_C. Values for the parameters are given in
Table 22,
SSP AC Timing Specifications
on page 44.
Figure 8. LCD AC Timing Definitions
Table 21. LCD AC Timing Specifications
Symbol
Description
Min
Max
Units
Notes
Tpclkdv
L_PCLK rise/fall to L_LDD<7:0> driven
valid
14
ns
1
Tpclklv
L_PCLK fall to L_LCLK driven valid
14
ns
2
Tpclkfv
L_PCLK fall to L_LFCLK driven valid
14
ns
2
Tpclkbv
L_PCLK rise to L_BIAS driven valid
14
ns
2
NOTES:
1. You can program the LCD data pins to be driven on either the rising or falling edge of the pixel clock
(L_PCLK).
2. These LCD signals can, at times, transition when L_PCLK is not clocking (between frames). At this time,
they are clocked with the internal version of the pixel clock before it is driven out onto the L_PCLK pin.
A4775-01
L_LDD[7:0]
(rise)
L_LDD[7:0]
(fall)
L_PCLK
L_LCLK
L_BIAS
L_FCLK
Tpclkdv
Tpclklv
Tpclkfv
Tpclkbv
Tpclkdv
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