參數(shù)資料
型號(hào)： PXA210
廠商： Intel Corp.
英文描述： Intel-R PXA250 and PXA210 Applications Processors
中文描述： 英特爾- R的PXA250和PXA210應(yīng)用處理器
文件頁(yè)數(shù)： 24/46頁(yè)
文件大小： 431K
代理商： PXA210
PXA250 and PXA210
—
Electrical, Mechanical, and Thermal Specification
24
Datasheet
Miscellaneous Pins
BOOT_SEL
[2:0]
IC
Boot select pins.
(input) Indicates type of boot device.
PWR_EN
OC
Power Enable for the power supply.
(output) When negated, it signals the power
supply to remove power because the system is entering Sleep Mode.
nBATT_FAULT
IC
Main Battery Fault.
(input) Signals that main battery is low or removed. Assertion
causes the PXA210 applications processor to enter Sleep Mode or force an
Imprecise Data Exception, which cannot be masked. The PXA210 applications
processor will not recognize a wakeup event while this signal is asserted.
nVDD_FAULT
IC
VDD Fault.
(input) Signals that the main power source is going out of regulation.
nVDD_FAULT causes the PXA210 applications processor to enter Sleep Mode or
force an Imprecise Data Exception, which cannot be masked. nVDD_FAULT is
ignored after a wakeup event until the power supply timer completes
(approximately 10 ms).
nRESET
IC
Hard reset.
(input) Level sensitive input used to start the processor from a known
address. Assertion causes the current instruction to terminate abnormally and
causes a reset. When nRESET is driven high, the processor starts execution from
address 0. nRESET must remain low until the power supply is stable and the
internal 3.6864 MHz oscillator has stabilized.
nRESET_OUT
Reset Out.
(output) Asserted when nRESET is asserted and deasserts after
nRESET is deasserted but before the first instruction fetch. nRESET_OUT is also
asserted for
“
soft
”
reset events: sleep, watchdog reset, or GPIO reset.
JTAG and Test Pins
nTRST
IC
JTAG Test Interface Reset. Resets the JTAG/Debug port. If JTAG/Debug is used,
drive nTRST from low to high either before or at the same time as nRESET. If
JTAG is not used, nTRST must be either tied to nRESET or tied low. Intel
recommends that a JTAG/Debug port be added to all systems for debug and
download. See Chapter 9 in the
“
Intel
PXA250 and PXA210 Applications
Processor Design Guide
”
for details.
TDI
IC
JTAG test data input.
(input) Data from the JTAG controller is sent to the PXA210
using this pin. This pin has an internal pull-up resistor.
TDO
OCZ
JTAG test data output.
(output) Data from the PXA210 applications processor is
returned to the JTAG controller using this pin.
TMS
IC
JTAG test mode select.
(input) Selects the test mode required from the JTAG
controller. This pin has an internal pull-up resistor.
TCK
IC
JTAG test clock.
(input) Clock for all transfers on the JTAG test interface.
TEST
IC
Test Mode.
(input) Reserved. Must be grounded.
TESTCLK
IC
Test Clock.
(input) Reserved. Must be grounded.
Power and Ground Pins
VCC
SUP
Positive supply for internal logic.
Must be connected to the low voltage (.85 -
1.3v) supply on the PCB.
VSS
SUP
Ground supply for internal logic.
Must be connected to the common ground
plane on the PCB.
PLL_VCC
SUP
Positive supply for PLLs and oscillators.
Must be connected to a separate quiet
supply plane on the PCB but may be connected to the common low voltage supply.
PLL_VSS
SUP
Ground signal for PLLs.
VCCQ
SUP
Positive supply for all CMOS I/O except memory bus.
Must be connected to the
common 3.3 V supply on the PCB.
Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 6 of 7)
Pin Name
Type
Signal Descriptions
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參數(shù)描述
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PXA250C0C400 制造商:Intel 功能描述:IC,MICROPROCESSOR,32-BIT,CMOS,BGA,256PIN,PLASTIC
PXA255 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:PXA255 Processor
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