參數(shù)資料
型號: PXA210
廠商: Intel Corp.
英文描述: Intel-R PXA250 and PXA210 Applications Processors
中文描述: 英特爾- R的PXA250和PXA210應用處理器
文件頁數(shù): 36/46頁
文件大?。?/td> 431K
代理商: PXA210
PXA250 and PXA210
Electrical, Mechanical, and Thermal Specification
36
Datasheet
Note:
If Hardware Reset is entered during Sleep Mode, follow the proper power-supply stabilization
times and nRESET timing requirements indicated in Table 13.
4.6.2
Hardware Reset Timing
The timing sequences shown in Hardware Reset Timing for hardware reset assumes stable power
supplies at the assertion of nRESET. If the power supplies are unstable, follow the timings
indicated in Section 4.6.1,
Power On Timing
on page 35.
Figure 4. Power-On Reset Timing
Table 13. Power-On Timing Specifications
Symbol
Description
Min
Typical
Max
Units
tR_BATT
BATT_VCC Rise / Stabilization time
0.01
100
ms
tR_VCCQ
VCCQ, VCCN Rise / Stabilization time
0.01
100
ms
tR_VCC
VCC, PLL_VCC Rise / Stabilization time
0.01
10
ms
tD_VCCQ
Delay between BATT_VCC at voltage
and before VCCQ and VCCN applied
0
ms
tD_VCC
Delay from VCCQ, VCCN at voltage and
before VCC, PLL_VCC applied
0
ms
tD_NTRST
Delay between VCC, PLL_VCC stable
and nTRST deasserted
50
ms
tD_JTAG
Delay between nTRST deasserted and
JTAG pins active, with nRESET asserted
0.03
ms
tD_NRESET
Delay between VCC, PLL_VCC stable
and nRESET deasserted
50
ms
tD_OUT
Delay between nRESET deasserted and
nRESET_OUT deasserted
18.1
18.2
ms
BATT_VCC
VCCQ
VCC
nTRST
JTAG PINS
nRESET
t
R_BA
T T
t
R_VCCQ
t
R_VCC
t
D_VCCQ
t
D_VCC
t
D_NTRST
t
D_JT
A G
t
D_NRESET
t
D_OUT
deasserted or the PXA250 applications processor enters Sleep Mode.
VCCN
t
R_VCC
N
t
D_VCC
N
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is
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