參數(shù)資料
型號(hào)： PWL6030B1AECMRR
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA187
封裝： 7 X 7 MM, 0.40 MM PITCH, GREEN, FCBGA-187
文件頁(yè)數(shù)： 49/97頁(yè)
文件大?。?/td> 937K
代理商： PWL6030B1AECMRR
SWCS045B
– SEPTEMBER 2010 – REVISED JUNE 2011
NOTE
Minimum values are defined at
–[1.50, 1.75]% of the nominal value.
Maximum values are defined at +[3.00, 3.25]% of the nominal value.
An hysteresis is implemented between the rising and falling edges, varying from 100
mV (VBAT = 2.050 V nominal) to 600 mV (VBAT = 3.100 V nominal).
The analog IP duplicates the VBATMIN_LO default value:
<000000> and <000110>
selection codes are identical (2.300 V nominal).
Because VBAT minimum level is defined as 2.3 V through the Phoenix power IC
specification, all codes between
<000001> and <000101> must not be used for the
correct operation of the device.
Reset Signals, Reset Triggers, Reset Domains
This section describes the different reset triggers and the signals related to resets.
Power-on reset: It is triggered when a low battery and a low backup battery condition occurs. This activates
a POR that remains active until a valid energy source is detected. The POR release initiates the boot
sequence of the TWL6030 device. A delayed version of POR is used in the charger and released during boot
sequence when the resources required by the charger are available. During a POR, the TWL6030 device is in
a NO SUPPLY state.
Warm reset (NRESWARM): The TWL6030 device detects a request for a warm reset on the NRESWARM
ball. The effect of the warm reset is to restart the system without turning off the supplies. After a warm reset,
the system is configured as it is after a first switch-on (default configuration), except that the states of all
resources are unchanged and all supply voltage values can be preserved, depending on the warm reset
sensitivity bit value (WR_S SMPS_CFG_VOLTAGE/LDO_CFG_VOLTAGE):
– All resources not included in the switch-on sequence keep the state (ON or OFF) they have just before the
warm reset.
– Depending on the sensitivity bit, those resources either keep the value they had before the warm reset or
are set to their default value.
– All resources included in the start-up sequence are restarted in any case.
During the power-on sequence, the TWL6030 device ignores the warm reset until the host processor releases
it.
Warmreset affects the POWER and CHARGER registers. Registers for other modules like the USB, FUEL
GAUGE, GPADC, and PWM are not affected by warmreset
Software reset: A cold reset can be initiated by software through the I2C control interface. The effect of this
software reset (the SW_RESET bit in the PHOENIX_DEV_ON register) forces the TWL6030 device to
perform a switch-off sequence (go to the WAIT-ON/OFF state). This is followed by a switch-on sequence
(WAIT-ON to ACTIVE).
Long key press: The long key press on PWRON generates a reset, thus forcing the TWL6030 device to go
into WAIT-ON/OFF state. The 10-second length is not configurable.
Primary watchdog reset: The TWL6030 device includes a primary watchdog timer, which generates a reset
of the system in case of a software anomaly (no response, infinite loop) (the DEVOFF_WDT bit in the
PHOENIX_LAST_TURNOFF_STS
register).
The
primary
watchdog
PRIMARY_WATCHDOG_CFG
is
programmable from 1 to 127 seconds with a default value of 32 seconds. In case the primary watchdog
expires, it generates a reset forcing the TWL6030 device to go into the WAIT-ON/OFF state. The watchdog is
initialized to its default value when the system is in WAIT-ON/OFF state and starts when leaving the
WAIT-ON/OFF state to the ACTIVE/SLEEP states. Software cannot disable the primary watchdog, which is
possible only through EPROM for testing purposes.
Thermal shutdown: If the die temperature gets too high, the thermal shutdown generates a reset, forcing the
TWL6030
device
into
the
WAIT-ON/OFF
state
(the
DEVOFF_TSHUT
bit
in
PHOENIX_LAST_TURNOFF_STS). See also the associated thermal shutdown registers: TMP_CFG_GRP,
TMP_CFG_TRANS, TMP_CFG_STATE, and TMP_CFG.
NRESPWRON: The NRESPWRON output signal is the reset signal delivered to the host processor at the end
of the power-on sequence. It is released when all TWL6030 supply voltages (core and I/Os) are correctly set
up. In addition, the NRESPWRON signal can be gated until the 32-kHz crystal oscillator becomes stable
(configured through an EPROM bit). The polarity of the NRESPWRON signal is active low.
Copyright
2010–2011, Texas Instruments Incorporated
53
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