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參數(shù)資料
| 型號： | PUMA2S1000M-35 |
| 元件分類： | SRAM |
| 英文描述： | 32K X 32 MULTI DEVICE SRAM MODULE, 35 ns, CHMA66 |
| 封裝： | CERAMIC, MODULE, PGA-66 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 555K |
| 代理商： | PUMA2S1000M-35 |
PUMA 2S1000 - 25/35/45
ISSUE 4.5 : August 2002
7
AC Write Characteristics Notes
(1) A write occurs during the overlap (t
WP) of a low CS and a low WE.
(2) t
WR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs
remain in a high impedance state.
(5) OE is continuously low. (OE=V
IL)
(6) Dout is in the same phase as written data of this write cycle.
(7) Dout is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied
to I/O pins.
(9) t
WHZ and tOHZ is defined as the time at which the outputs achieve the open circuit conditions and is not referenced
to output voltage levels. This parameter is sampled and not 100% tested.
CS and WE above refer to CS1~4 and WE1~4 respectively.
Data Retention Waveform
CDR
R
t
4.5V
2.2V
0V
DATA RETENTION MODE
Vcc
CS1~4
V
DR
CS1~4>Vcc-0.2V
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| PUMA2S1000M-45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SRAM|32KX32|CMOS|PGA|66PIN|CERAMIC |
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