- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69258 > PTPS659105A1RSLR (TEXAS INSTRUMENTS INC) POWER SUPPLY SUPPORT CKT, PQCC48 PDF資料下載
參數(shù)資料
| 型號： | PTPS659105A1RSLR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48 |
| 文件頁數(shù)： | 79/89頁 |
| 文件大?。?/td> | 941K |
| 代理商： | PTPS659105A1RSLR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁當(dāng)前第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁
PRODUCTPREVIEW
SWCS046C – MARCH 2010 – REVISED JUNE 2010
www.ti.com
Table 71. EN3_LDO_ASS_REG
Address Offset
0x49
Physical Address
Instance
Description
Configuration Register setting the LDO regulators, driven by the EN3 signal.
When control bit = 1, LDO regulator state is driven by the EN3 control signal and is also defined though
SLEEP_KEEP_LDO_ON register setting:
When EN3 is high the regulator is on,
When EN3 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low power mode if its corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the
device state.
Type
RW
7
6
5
4
3
2
1
0
VDAC_EN3
VPLL_EN3
VAUX33_EN3
VAUX2_EN3
VAUX1_EN3
VDIG2_EN3
VDIG1_EN3
VMMC_EN3
Bits
Field Name
Description
Type
Reset
7
VDAC_EN3
Setting supply state control though EN3 signal
RW
0
6
VPLL_EN3
Setting supply state control though EN3 signal
RW
0
5
VAUX33_EN3
Setting supply state control though EN3 signal
RW
0
4
VAUX2_EN3
Setting supply state control though EN3 signal
RW
0
3
VAUX1_EN3
Setting supply state control though EN3 signal
RW
0
2
VDIG2_EN3
Setting supply state control though EN3 signal
RW
0
1
VDIG1_EN3
Setting supply state control though EN3 signal
RW
0
VMMC_EN3
Setting supply state control though EN3 signal
RW
0
Table 72. SPARE_REG
Address Offset
0x4A
Physical Address
Instance
Description
Spare functional register
Type
RW
7
6
5
4
3
2
1
0
SPARE
Bits
Field Name
Description
Type
Reset
7:0
SPARE
Spare bits
RW
0x00
Table 73. INT_STS_REG
Address Offset
0x50
Physical Address
Instance
Description
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type
RW
80
Copyright 2010, Texas Instruments Incorporated
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PTPS659103A1RSL | POWER SUPPLY SUPPORT CKT, PQCC48 |
| PTPS659108A1RSLR | POWER SUPPLY SUPPORT CKT, PQCC48 |
| PTPS659106A1RSL | POWER SUPPLY SUPPORT CKT, PQCC48 |
| PTPS659108A1RSL | POWER SUPPLY SUPPORT CKT, PQCC48 |
| PTPS659101A1RSL | POWER SUPPLY SUPPORT CKT, PQCC48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PTPS659109A1RSL | 制造商:Texas Instruments 功能描述: |
| PTPS6591102A2ZRCR | 制造商:TI 功能描述:TPS65911 |
| PTPS6591102ZRC | 制造商:TI 功能描述:TPS65911 |
| PTPS6591104A2ZRCR | 制造商:TI 功能描述:TPS65911 |
| PTPS659110A2ZRC | 制造商:TI 功能描述:TPS65911 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。