參數(shù)資料
型號： PTPS659105A1RSLR
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC48
封裝： 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48
文件頁數(shù)： 37/89頁
文件大?。?/td> 941K
代理商： PTPS659105A1RSLR
PRODUCTPREVIEW
SWCS046C – MARCH 2010 – REVISED JUNE 2010
www.ti.com
Resources can be kept in their active mode: (full-load capability), programming the SLEEP_KEEP_LDO_ON and
the SLEEP_KEEP_RES_ON registers. These registers contain 1 bit per power resource. If the bit is set to 1,
then that resource stays in active mode when the device is in SLEEP state. 32KCLKOUT is also included in the
SLEEP_KEEP_RES_ON register and the 32-kHz clock output is maintained in SLEEP state if the corresponding
mask bit is set.
PWRHOLD
When none of the device power-on disable conditions are met, a rising edge of this signal causes an
OFF-to-ACTIVE state transition of the device and a falling edge causes a transition back to OFF state. Typically,
this signal is used to control the device in a slave configuration. It can be connected to the SYSEN output signal
from other TPS659xx devices, or the NRESPWRON signal of another TPS65910 device. This input signal is
level sensitive and no debouncing is applied.
A rising edge of PWRHOLD is highlighted though an associated interrupt.
BOOT0/BOOT1
These signals determine which processor the device is working with and hence which power-up sequence is
needed. See SWITCH-ON/-OFF SEQUENCES AND TIMING for more details. There is no debouncing on this
input signal.
NRESPWRON
This signal is used as the reset to the processor. It is held low until the ACTIVE state is reached. See POWER
CONTROL TIMING to get detailed timing.
CLK32KOUT
This signal is the output of the 32-K oscillator, which can be enabled or not during the power-on sequence,
depending on the Boot mode. It can be enabled and disabled by register bit, during ACTIVE state of the device.
CLK32KOUT output can also be enabled or not during SLEEP state of the device depending on the
SLEEPMASK register programming.
PWRON
The PWRON input is connected to an external button. A debounced falling edge on this signal causes an
OFF-to-ACTIVE state or SLEEP-to-ACTIVE state transition of the device. If the device is in Active mode then a
low level on this signal generates an interrupt.
If the PWRON signal is low for more than the PWON_TO_OFF_DELAY delay and the corresponding interrupt is
not acknowledged by the external processor, the device goes into OFF state.
INT1
INT1 signal (default active low) warns the host processor of any event that occurred on the TPS65910 device.
The host processor can then poll the interrupt from the interrupt status register through I2C to identify the
interrupt source. A low level (default setting) indicates an active interrupt, highlighted in the INT_STS_REG
register. The polarity of INT1 can be set by programming the IT_POL control bit. INT1 flag active is a POWER
ON enable condition during a fixed delay tDOINT1 (only) when the device is in OFF state (when NRESPWON
signal is low). Any of the interrupt sources can be masked by programming the INT_MSK_REG register. When
an interrupt is masked, its corresponding interrupt status bit is still updated, but the INT1 flag is not activated.
interrupt source masking can be used to mask a device switch-on event. Because interrupt flag active is a
POWER ON enable condition during tDOINT1 delay, any interrupt not masked must be cleared to allow immediate
turn off of the device. See section: Interrupts, for interrupt sources definition.
SDASR_EN2 and SCLSR_EN1
SDASR_EN2 and SCLSR_EN1 are the data and clock signals of the serial control interface (SR-I2C) dedicated
to SmartReflex applications. These signals can also be programmed to be used as enable signals of one or
several supplies, when the device is on (NRESPWON high). A resource assigned to SDASR_EN2 or
SCLSR_EN1 control automaticaly disables the serial control interface.
42
Copyright 2010, Texas Instruments Incorporated
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