參數(shù)資料
型號(hào)： PT8R1202
廠商： Electronic Theatre Controls, Inc.
英文描述： Bluetooth Digital Audio Streaming IC
中文描述： 藍(lán)牙技術(shù)的數(shù)字音頻集成電路
文件頁數(shù)： 6/26頁
文件大?。?/td> 656K
代理商： PT8R1202
PT0137(08/04)
Ver:4
6
Data Sheet
PT8R1202
PT
Peric om Technology Inc .
Bluetooth Digital Audio Streaming IC
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Pin Descriptions
Pin Name
DI(Digital Input, 3.3V), DO(Digital Output, 3.3V), DB(Digital Bidirectional, 3.3V), DP(Digital Programmable, 3.3V)
DCP(Digital Core Power, 1.8V), DPP(Digital Peripheral Power, 3.3V)
DCG(Digital Core Ground), DPG(Digital Peripheral Ground)
AAI(Analog Audio Input, 3.3V), AAO(Analog Audio Output, 3.3V), AAB(Analog Audio Bidirectional, 3.3V)
ACI(Analog Core Input, 1.8V), ACO(Analog Core Output, 1.8V), ACB(Analog Core Bidirectional, 1.8V)
AAP(Analog Audio Power, 3.3V), AAG(Analog Audio Ground)
ACP(Analog Core Power, 1.8V), ACG(Analog Core Ground)
BLUETOOTH INTERFACE : 12
TXACTIVE / GPA[0]
D4
DO/ DP
active high
RXACTIVE / GPA[1]
C1
DO / DP
active high
TXDATA_EN / GPA[2]
E2
DO / DP
active high
TXDATA / GPA[3]
D1
DB / DP
serial data
RXDATA / GPA[4]
E3
DI / DP
serial data
SYNCDECTECT / GPA[5]
E1
DB / DP
active high
DATACLK / GPA[6]
F1
DI / DP
clock
RFRESET / GPA[7]
F3
DO / DP
active high
BLUERF_TCK / GPA[8]
F2
DO / DP
clock
BLUERF_TMS / GPA[9]
G3
DO / DP
serial data
BLUERF_TDI / GPA[10]
G1
DB / DP
serial data
BLUERF_TDO / GPA[11]
G2
DI / DP
serial data
CLOCK SIGNAL INTERFACE : 6
XTALIN
J8
DI
clock
XTALOUT
L9
DO
clock
PIN
I/O
TYPE
Description
transmitter enable
receiver enable
timing reference of valid data
transmit data
receive data
indication of SYNC word detection
Phy reference data clock
Reset signal for external radio transceiver
a serial register interface clock
control signal of Phy’s TAP controller
Phy control register serial data output
Phy control register serial data input
Crystal input for on-chip PLL (see note1)
Crystal output
PLL mode control (see note1)
External, test clock input (see note1, 2)
PLL mode control (see note1)
Manufacturing test mode (see note2)
External clock source select signal (see note1,2)
clock out divided by a third of internal system clock (see note1)
PLL_MD1
M10
DI
control
PLL_MD0
M11
DI / DO
control
PLLSEL
CLKOUT / GPB[0]
TEST & DEBUG INTERFACE : 9
RESET
BTMD[1:0]
SCAN_EN
JTAG_TCK / GPC[4]
JTAG_TMS / GPC[5]
JTAG_RST / GPC[6]
JTAG_TDI / GPC[7]
JTAG_TDO / GPC[8]
EXTERNAL MEMORY INTERFACE : 45
MEMA[19:0]
MEMD[15:0]
WEB
REB
UBE / GPB[1]
LBE / GPB[2]
FLASHCSB / GPB[3]
SRAMCSB / GPB[4]
IOCSB0 / GPB[5]
IOCSB1 / SM_CSB1 / GPB[6]
IOWAIT / GPB[7]
UART & USB INTERFACE : 6
UARTTX / GPC[0]
UARTRX / GPC[1]
DIGAMP_L / UARTRTS /
AUDISCLK / GPC[2]
DIGAMP_R / UARTCTS /
AUDILRCLK / GPC[3]
D+
D-
L10
L7
DI
DO / DP
control pin
clock
K8
DI
DI / DP
DI
DI / DP
DI / DP
DI / DP
DI / DP
DO / DP
active low
control pin
control pin
clock
serial data
active low
serial data
serial data
reset signal
boot mode (see note2)
manufacturing test (see note3)
JTAG clock signal
JTAG test mode signal
JTAG reset signal
JTAG serial input data
JTAG serial output data
M7, J7
C5
M8
K7
L8
K9
M9
(see note4)
(see note5)
C10
C12
D11
D10
D12
E10
E11
E12
F10
DO
DB
DO
DO
DO / DP
DO / DP
DO
DO / DP
DO / DP
DO / DP
DI / DP
bus
bus
active low
active low
active low
active low
active low
active low
active low
active low
control pin
address bus for external memory
data bus for external memory
write enable signal for external memory
read enable signal for external memory
upper byte enable (see note6)
lower byte enable (see note6)
chip select for external flash memory
chip select for external SRAM memory
chip select for external I/O device0
chip select for external I/O device1 (see note7)
IO wait cycle extension indication signal
H3
H1
DO / DP
DI / DP
serial data
serial data
UART serial transmit data / USBOE
UART serial receive data / USBSPEED
UART RTS(Ready To Send) signal / USBVPO
AUDISCLK / DIGAMP_L (see note8)
UART CTS(Clear To Send) signal / USBVMO
AUDILRCLK / DIGAMP_R(see note8)
USB D+
USB D-
H2
DO / DP
active low
J4
DO / DP
active low
B4
A4
DB
DB
serial data
serial data
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