PT0137(08/04)

Ver:4

22

Data Sheet

PT8R1202

PT

Peric om Technology Inc .

Bluetooth Digital Audio Streaming IC

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JTAG interface

PT8R1202 supports IEEE1149.1 standard specification compliant interface. This interface supports basic test commands such as

EXTEST, SMAPLE, BYPASS, and IDCODE. Beside of this, JTAG interface can be used communication channel with PTI

enhanced on-chip hardware debugger controller. Using on-chip debugger controller, off-chip debug handler or external host can

access internal peripheral device registers, external memory interface, and executes real-timing hardware debugging and

monitoring of on-chip embedded RISC processor. Also, external host can communicate on-chip RISC processor through JTAG

with on-chip hardware managed channel buffer. There are sixteen debug registers specified and these will be used in PTI own

development chip manager software, named as V6EMU. The length of instruction register in JTAG interface is 6bit and that

of debug data register is 32bit. Table 11. shows the summary of TAP instructions supported in PT8R1202 and Table 12. shows

the summary of debugger registers in JTAG interface.

Table 11. TAP instructions

Instruction

EXTEST

Opcode

0x000000

Description

EXTEST initiates testing of external circuitry, typically board-level interconnects and off chip

circuitry. EXTEST connects the Boundary-Scan register between TDI and TDO in the SHIFT_DR

state only. When EXTEXT is selected, all output signal pin values are driven by values shifted into

the Boundary-Scan register and may change only on the falling-edge of TCK in the Update_DR

state. Also, when EXTEST is selected, all system input pin states must be loaded into the

Boundary-Scan register on the rising-edge of TCK in the Capture_DR state. Values shifted into

input latches in the Boundary-Scan register are never used by the processor’s internal logic.

SAMPLE / PRELOAD performs two functions:

When the TAP controller is in the Capture-DR state, the SAMPLE instruction occurs on the

rising edge of TCK and provides a snapshot of the component’s normal operation without

interfering with that normal operation. The instruction causes Boundary-Scan register cells

associated with outputs to SAMPLE the value being driven by or to the processor.

When the TAP controller is in the Update-DR state, the PRELOAD instruction occurs on the

falling edge of TCK. This instruction causes the transfer of data held in the Boundary-Scan cells to

the slave register cells. Typically the slave latched data is then applied to the system outputs by

means of the EXTEST instruction.

IDCODE is used in conjunction with the device identification register. It connects the

identification register between TDI and TDO in the Shift_DR state. When selected, IDCODE

parallel-loads the hard-wired identification code (32 bits) on TDO into the identification register on

the rising edge of TCK in the Capture_DR state.

NOTE: The device identification register is not altered by data being shifted in on TDI.

DEBUG instruction select the DEBUGReg with address indicator SSSS.

When the TAP controller is in the Capture-DR state, the DEBUG instruction occurs on the rising

edge of TCK and executes a snapshot of DEBUG register addressed SSSS into DEBUGReg.

When the TAP controller is in the Update-DR state, the DEBUG instruction occurs on the falling

edge of TCK. This instruction causes the transfer of data held in DEBUGReg to DEBUG register

addressed SSSS.

BYPASS instruction selects the Bypass register between TDI and TDO pins while in SHIFT_DR

state, effectively bypassing the processor’s test logic. 0 is captured in the CAPTURE_DR state.

While this instruction is in effect, all other test data registers have no effect on the operation of the

system. Test data registers with both test and system functionality perform their system functions

when this instruction is selected

SAMPLE

0x000001

IDCODE

0x011111

DEBUG

(Private Instruction)

0x10SSSS

BYPASS

0x111111

Table 12. Debug interface register address map

Address

0x0

0x1

0x2

0x3

0x4

0x5

Name

DEBUG_CMD

DEBUG_CTRL

DEBUG_TX

DEBUG_RX

DEBUG_ADDR

DEBUG_WDATA0

(DEBUG_CYC_CNT)

DEBUG_RDATA0

DEBUG_INST_ACNT

DEBUG_INST_SCNT

DEBUG_BREAK_PC

Attribute

Write

Read

Read

Write

Write

Write

Description

debugger control register

debug handler control register

debug handler transmit register

debug handler receive register

debugger address register

debugger write data register0(31:0)

debugger instruction step count

debugger read data register0(31:0)

debugger instruction cycle accumulator

debugger instruction step cycle count

debugger breakpoint PC register

0x7

0x9

0xA

0xB

Read

Read

Read

Write