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參數(shù)資料
| 型號(hào)： | PSD813F |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System-Programmable Microcontroller Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM) |
| 中文描述： | Flash在系統(tǒng)可編程微控制器外圍設(shè)備（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬(wàn)位閃速存儲(chǔ)器，256K位的EEPROM，16K的位的SRAM） |
| 文件頁(yè)數(shù)： | 15/130頁(yè) |
| 文件大小： | 650K |
| 代理商： | PSD813F |
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Prelimnary
PSD813F Famly
11
Pin Name Pin* Type
Description
CNTL2
49
I
This port can be used to input the PSEN (Program Select
Enable) signal from any MCU that uses this signal for code
exclusively. If your MCU does not output a Program Select
Enable signal, this port can be used as a generic input. This
port is connected to the PLDs.
Active low reset input. Resets I/O Ports, PLD Micro
Cells
and some of the configuration registers. Must be active at
power up.
These pins make up Port A. These port pins are configurable
and can have the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro
Cell (McellAB0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 6).
5. Address inputs. For example, PA0-3 could be used for
A[0:3] when using an 80C51XA in burst mode.
6. As the data bus inputs D[0:7] for non-multiplexed
address/data bus MCUs.
7. D0/A16-D3/A19 in M37702M2 mode.
8. Peripheral I/O mode.
Note:
PA0-3 can only output CMOS signals with an option
for high slew rate. However, PA4-7 can be configured as
CMOS or Open Drain Outputs.
These pins make up Port B. These port pins are configurable
and can have the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro
Cell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs.
4. Latched address outputs (see Table 6).
Note:
PB0-3 can only output CMOS signals with an option
for high slew rate. However, PB4-7 can be configured as
CMOS or Open Drain Outputs.
PC0 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro
Cell (McellBC0) output.
3. Input to the PLDs.
4. TMS Input** for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. CPLD Micro
Cell (McellBC1) output.
3. Input to the PLDs.
4. TCK Input** for the JTAG Interface.
This pin can be configured as a CMOS or Open Drain output.
Reset
48
I
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
I/O
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
I/O
52
51
PC0
20
I/O
PC1
19
I/O
Table 5.
PSD813F
Pin
Descriptions
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD813FH(中文) | Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場(chǎng)可編程微控制器) |
| PSD813FN(中文) | Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場(chǎng)可編程微控制器) |
| PSD813FN | Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場(chǎng)可編程微控制器) |
| PSD813FH | Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場(chǎng)可編程微控制器) |
| PSD82 | Three Phase Rectifier Bridges |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD813F1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F1A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V |
| PSD813F1-A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F1A-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD813F1-A-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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