參數(shù)資料
型號(hào): PSD813F2A
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable(ISP) Peripherals For 8-bit MCUs(用于八位MCU的閃速在系統(tǒng)可編程外圍芯片)
中文描述: Flash在系統(tǒng)可編程(ISP)為周邊8位微控制器(用于八位微控制器的閃速在系統(tǒng)可編程外圍芯片)
文件頁數(shù): 93/103頁
文件大小: 1180K
代理商: PSD813F2A
93/103
PSD8XXF2/3/4/5
Figure 46. Reset (RESET) Timing
Table 64. Reset (RESET) Timing (5V devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 65. Reset (RESET) Timing (3V devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 66. V
STBYON
Timing (5V devices)
Symbol
Note: 1. V
STBYON
timing is measured at V
CC
ramp rate of 2 ms.
Table 67. V
STBYON
Timing (3V devices)
Symbol
Note: 1. V
STBYON
timing is measured at V
CC
ramp rate of 2 ms.
Symbol
Parameter
Conditions
Min
Max
Unit
t
NLNH
RESET Active Low Time
1
150
ns
t
NLNH–PO
Power On Reset Active Low Time
1
ms
t
NLNH–A
Warm Reset (on the PSD834Fx)
2
25
μ
s
t
OPR
RESET High to Operational Device
120
ns
Symbol
Parameter
Conditions
Min
Max
Unit
t
NLNH
RESET Active Low Time
1
300
ns
t
NLNH–PO
Power On Reset Active Low Time
1
ms
t
NLNH–A
Warm Reset (on the PSD834Fx)
2
25
μ
s
t
OPR
RESET High to Operational Device
300
ns
Parameter
Conditions
Min
Typ
Max
Unit
t
BVBH
V
STBY
Detection to V
STBYON
Output High
(Note
1
)
20
μs
t
BXBL
V
STBY
Off Detection to V
STBYON
Output
Low
(Note
1
)
20
μs
Parameter
Conditions
Min
Typ
Max
Unit
t
BVBH
V
STBY
Detection to V
STBYON
Output High
(Note
1
)
20
μs
t
BXBL
V
STBY
Off Detection to V
STBYON
Output
Low
(Note
1
)
20
μs
tNLNH-PO
Power-On Reset
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
Warm Reset
tOPR
V
CC
V
CC
(min)
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