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參數(shù)資料
| 型號(hào)： | PSD703S5 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個(gè)可編程輸入/輸出，通用PLD的有66個(gè)輸入） |
| 文件頁(yè)數(shù)： | 72/104頁(yè) |
| 文件大?。?/td> | 515K |
| 代理商： | PSD703S5 |
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PSD7XX Family
13-72
Reset
Debouncer
Clock
Clock Source
WatchDog Timer Clock
Pulse Generator Clock
Timeout
Periods
Pulse Width
(ms)
Frequency
Frequency
Frequency
Internal
Oscillator
2KHz
2KHz/16
2KHz or
2KHz/256
From 0.5ms
to 63.875s
(0.5ms
increment)
2KHz/2
8,16,32,64,
128,256,512
External
Clock CLKIN
CLKIN/128K
CLKIN/8K
or
CLKIN/2M
Depends on
CLKIN
Frequency
CLKIN/16K
Depends on
CLKIN
Frequency
Table 39. Clock Sources
Clock Source and Frequency Selection
With the exception of the Digital Sampler which has a dedicated 32KHz internal oscillator,
all other Supervisory circuitry can run on either the 2KHz internal oscillator or the external
CLKIN input.
Table 39 shows the available clock sources and clock inputs to the different circuitry.
Based on the selected clock source, the PSDsoft Design Tool provides the user with
programmable WatchDog timeout periods and reset pulse widths.
PSD7XX
RESET
RESET
RST–OUT PC1
VSTBY PC2
CEOUT PC3
VSTBY ON PC4
RST–OUT PC5
V
tp
PC6
NON-VOLATILE
WRITABLE
MEMORY
(BATTERY BACKED
SRAM, FLASH,
EEPROM, etc.)
CE
TYPICAL
MICROCONTROLLER
BATTERY
FOR SRAM
BACKUP
V
CC
V
CC
N.O.
MOMENTARY
26.8K
10K
Reset signal is
active for WatchDog
timeout, or V
CC
drop,
or pushbutton
activation.
*
*
V = 1.29V
WHEN
V
CC
= 4.75V
Figure 33. Supervisory Functions
Supervisory
Function
(cont.)
The figure above shows optional usage of the supervisory functions. These features
are included in this diagram: reset input debounce, external trip voltage configuration,
external nonvolatile writable memory, and external standby power source.
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