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| 型號： | PSD703S5 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備具有監(jiān)督職能（可編程邏輯，4K的位的SRAM，27余個可編程輸入/輸出，通用PLD的有66個輸入） |
| 文件頁數(shù)： | 46/104頁 |
| 文件大?。?/td> | 515K |
| 代理商： | PSD703S5 |
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PSD7XX Family
13-46
I/O Ports
(cont.)
Port Operating Modes
(cont.)
Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Port A, B, or C. The address input can be latched in the Input Micro
Cell by
ALE. Any input that is included in the DPLD equations for the PSD EPROM and SRAM is
considered as address input.
Data Port Mode
Port A and B can be used as data bus ports for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port A or B if the port is configured as Data Port.
Supervisory Function Mode
Port C (pins PC1–PC6) can be configured to implement the Supervisory Function.
Refer to the Supervisory section for a detailed description.
Peripheral I/O Mode
Only Port A supports the Peripheral I/O mode where all of Port A I/O serves as a
tri-state capable bi-directional data buffer of the microcontroller’s data bus. Peripheral mode
is enabled by setting Bit 7 of the VM Register to a “1”. Figure 22 shows that when
Peripheral mode is enabled and either PSEL0 and PSEL1 from the DPLD is active, Port A
acts as a bi-directional buffer for the microcontroller D[7:0] data bus. The buffer is tri-stated
when PSEL 0 or 1 is not active. The Peripheral I/O mode can be used to interface with
external peripherals.
Open Drain/Slew Rate Mode
Ports A (pins PA7-4) and B (pins PB7-4) and C can be configured as an open drain instead
of CMOS outputs. The Open Drain configuration is useful for sinking large currents
to operate LEDs, for example. The Open Drain mode is enabled by writing a “1” to the
corresponding bit in the Drive Register.
Port A (PA3–0), Port B (PB3–0) and Port D can be configured as ECSPLD outputs that
have a high slew rate. The high slew rate is enabled by writing a “1” to the corresponding
bit in the Drive Register.
RD
PSEL0
PSEL1
VM REGISTER BIT 7
WR
PA0-PA7
D0-D7
DATA BUS
Figure 22. Port A Peripheral Mode
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