參數(shù)資料
型號(hào): PSD611E1
英文描述: Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞(可編程邏輯,4K的位的SRAM,26我個(gè)可編程輸入/輸出,通用PLD的有63個(gè)輸入)
文件頁數(shù): 7/84頁
文件大小: 426K
代理商: PSD611E1
PSD6XX Family
11-7
Tables 4 and 4A show the offset address to the PSD6XXE1 registers relative to the CSIOP
base address. The CSIOP space is the 256 bytes of address that is allocated by the user to
the internal PSD6XXE1 registers. Some Motorola 16-bit microcontrollers, including the
M68HC16, M68302 and M683XX, have a different data byte orientation requiring separate
address offset maps.
Table 4 shows the CSIOP address offsets for all MCUs except those from Motorola in 16-bit
mode. Table 4A shows the address offsets for Motorola MCUs in 16-bit mode.
PSD6XXE1
Register
Description
and Address
Offset
Register Name
Port A Port B Port C Port D Other*
Description
Data In
00
01
10
11
Reads Port pin as input,
MCU I/O input mode
Control
02
03
Selects mode between
MCU I/O or Address Out
Data Out
04
05
12
13
Stores data for output
to Port pins, MCU I/O
output mode
Direction
06
07
14
15
Configures Port pin as
input or output
Drive
08
09
16
17
Configures Port pin
between CMOS,
Open Drain and
Slew rate
Input Micro
Cell
0A
0B
18
Reads Input Micro
Cell
Enable Out
0C
0D
1A
Reads the status of the
output enable to the I/O
Port driver
Output
Micro
Cell
20
20
21
Read – reads output of
Micro
Cells
(McellC, McellAB)
Write – loads Micro
cell
Flip-Flops
PMMR0
B0
Power Management
Register 0
PMMR1
B2
Power Management
Register 1
Page
E0
Page Register
VM
E2
8031/PIO Configuration
Register
Table 4. Register Address Offset
*
Other registers that are not part of the I/O ports.
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