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| 型號： | PSD501B1 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| 中文描述： | 現場可編程微控制器外圍設備（可編程邏輯，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入） |
| 文件頁數： | 24/130頁 |
| 文件大小： | 704K |
| 代理商： | PSD501B1 |
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PSD5XX Famly
6-24
The PPLD
The Peripheral Programmable Logic Device (PPLD) provides a powerful mechanism for
the user to control the operations of the Counter/Timer and Interrupt Controller. Figure 11 is
the PPLD block diagram. There are six Peripheral Macrocells, four are dedicated to the
Counter/Timer, and two to the Interrupt Controller.
The outputs from the four Peripheral Macrocells, MC2TMR[3:0], are used as
load/store/enable inputs to the Counter/Timer (multiplexed with pin inputs TIMER[3:0]_IN).
The remaining two macrocell outputs (MC2INT[6:7]), together with two other product terms
(PT2INT4, PT2INT5), can generate up to 4 user defined interrupts to the Interrupt
Controller. The watch-dog output of the Timer (WDOG2PLD) and Interrupt Controller
(INTR2PLD) are available as inputs to the ZPLD’s AND ARRAY.
The structure of a Peripheral Macrocell is shown in Figure 12. The cell has two product term
inputs from the AND ARRAY. The user can select the registered or combinatorial output of
the macrocell, as well as the output polarity. The registers are clocked by the CLKIN clock,
and are cleared by the RESET input during power up.
The ZPLD
Power
Management
The ZPLD implements a Zero Power Mode, which provides considerable power savings
for low to medium frequency operations. To enable this feature, the ZPLD Turbo bit in the
Power Management Mode Register 0 (PMMR0) has to be turned off.
If none of the 61 inputs to the ZPLD are switching for a time period of 70ns, the ZPLD puts
itself into Zero Power Mode and the current consumption is minimal. The ZPLD will resume
normal operation as soon as one or more of the inputs change state.
Two other features of the ZPLD provide additional power savings:
1. Clock Disable:
Users can disable the clock input to the ZPLD and/or macrocells, thereby reducing AC
power consumption.
2. Product Term Disable:
Unused product terms in the ZPLD are disabled by the PSDsoft Software automatically
for further power savings.
The ZPLD power configuration is described in the Power Management Unit section.
ZPLDBlock
(Cont.)
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| PSD511B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| PSD502B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| PSD503B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
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相關代理商/技術參數 |
參數描述 |
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| PSD501B1-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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