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| 型號(hào)： | PSD501B1 |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有61個(gè)輸入） |
| 文件頁(yè)數(shù)： | 2/130頁(yè) |
| 文件大?。?/td> | 704K |
| 代理商： | PSD501B1 |
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PSD5XX Famly
6-2
Key Features
(Cont.)
J
A security bit prevents reading the PSD5XX configuration, ZPLD and EPROM contents.
This inhibits copying the device on a programmer.
J
Port A can be used as a buffered microcontroller data bus (Peripheral I/O Mode) of the
microcontroller bus. This provides easy access to sub-systems that require more drive
on the data bus or accessing a resource that is shared by another MCU or DMA
Controller.
J
Low power operation is achieved by using a Power Management Unit (PMU) that enables
automatic standby modes in the EPROM, SRAM, and ZPLDs. It also disables the clock
to the ZPLD and Counter/Timer. Also available is an automatic power down mode using
the ALE signal. A Sleep mode is available that consumes only 10 μA standby power
consumption.
J
PSD5XX standard versions are ideal for general purpose applications.
J
PSD5XXM mask-programmable versions are ideal for code-stable, high-volume
low cost applications.
J
Package choices include 68 pin plastic (J) and ceramic (L) chip carriers.
J
The PSD5XX family is supported with PC based PSDsoft
MS-Windows
compatible
development tools. Offering ABEL
as a design entry method, (PSDabel
), an
efficient Fitter, Address Translator, MagicPro
programmer and a full chip simulator
(PSDsilos III
) are included.
The PSD5XX series of Field Programmable Microcontroller Peripherals represent a major
advance in the evolution of Programmable Peripherals. They combine an innovative
architecture with state of the art technology to provide user programmability (logic,
functions, memory), flexibility, high integration, optimum performance, low power . For
example, the PSD513B1 can implement a full peripheral subsystem and has the following
features:
J
Three ZPLDs with a total of 61 inputs, 140 product terms outputs, 30 macrocells and
24 I/O pins.
J
40 individually programmable I/O pins that are divided into 5 Ports.
J
Four 16-bit Peripheral PLD (PPLD)-controlled Counter/Timers that can perform pulse,
waveform, time capture, event counting and watch dog functions.
J
Eight input priority encoded Interrupt Controller. Four interrupts are generated by the
Counter/Timer unit and the other four can be user defined through the PPLD.
J
4-Bit Page Register
J
1 Mbit Reprogrammable EPROM consists of four 256 Kbit blocks.
J
16 Kbit of standby SRAM that can automatically switch into standby mode.
J
Power management unit with automatic standby and sleep modes.
J
Security mode.
Figure 1 is a top level block diagram of the PSD5XX. Refer to Table 1 and other sections
for details on functionality, DC/AC specification, packages and ordering information.
General
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD511B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| PSD502B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| PSD503B1 | Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入) |
| PSD502B1-12U | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-204AE package; Similar to IRH7250 with optional Total Dose Rating of 1000kRads |
| PSD502B1-12UI | 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-254AA package; A IRHM57264SE with Standard Packaging |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD501B1-12J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD501B1-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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