參數(shù)資料
型號(hào): PSD4235G2-A-12J
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的16位微控制器5V電源
文件頁(yè)數(shù): 58/89頁(yè)
文件大?。?/td> 703K
代理商: PSD4235G2-A-12J
PSD4235G2
58/89
Figure 31. Port E, F and G Structure
Port F – Functionality and Structure
Port F can be configured to perform one or more
of the following functions:
I
MCU I/O Mode
I
CPLD Output – External Chip Select (ECS7-
ECS0) can be connected to Port F or Port C.
I
CPLD Input – direct input to the CPLD, no Input
Macrocells (IMC)
I
Latched Address output – Provide latched
address output as per Table 41.
I
Slew Rate – pins can be configured for fast Slew
Rate
I
Data Port – connected to D7-D0 when Port F is
configured as Data Port for a non-multiplexed
bus
I
Peripheral Mode
I
MCU Reset Mode – for 16-bit Motorola 683xx
and HC16 MCUs
Port G – Functionality and Structure
Port G can be configured to perform one or more
of the following functions:
I
MCU I/O Mode
I
L
atched Address output – Provide latched
address output as per Table 41.
I
Open Drain – pins can be configured in Open
Drain Mode
I
Data Port – connected to D15-D8 when Port G
is configured as Data Port for a non-multiplexed
bus
I
MCU Reset Mode – for 16-bit Motorola 683xx
and HC16 MCUs
I
DATA OUT
Register
D
Q
D
G
Q
D
Q
D
Q
WR
WR
WR
ADDRESS
Ext. CS (Port F)
ENABLE PRODUCT TERM (.OE)
ALE
READ MUX
P
D
B
CPLD-INPUT (Port F)
CONTROL Register
DIR Register
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT Pin
DATA OUT
ADDRESS
A[7:0] OR A[15:8]
AI04938
ISP or Battery Back-Up (Port E)
Configuration Bit
相關(guān)PDF資料
PDF描述
PSD4235G1-12B81 Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G1-12B81I Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G1-12J Flash In-System-Programmable Peripherals for 16-Bit MCUs
PSD4235G1V-12MI Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply
PSD4235G1V-12U Flash In-System-Programmable Peripherals for 16-Bit MCUs
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