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參數(shù)資料
| 型號： | PSD4235G1-12J |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器 |
| 文件頁數(shù)： | 25/89頁 |
| 文件大?。?/td> | 703K |
| 代理商： | PSD4235G1-12J |
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PSD4235G2
Sector Erase cycle for a period of 100
μs + 20%
unless an additional Sector Erase instruction is de-
coded. After this period, or when the additional
Sector Erase instruction is decoded, the Erase
Time-out Flag (DQ3/DQ11) bit is set to 1.
Programming Flash Memory
Flash memory must be erased prior to being pro-
grammed. The MCU may erase Flash memory all
at once or by-sector. Although erasing Flash mem-
ory occurs on a sector or device basis, program-
ming Flash memory occurs on a word basis.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
word or to erase sectors (see Table 29).
Once the MCU issues a Flash memory Program or
Erase instruction, it must check the status bits for
completion. The embedded algorithms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PE4) signal.
Data Polling.
Polling on the Data Polling (DQ7/
DQ15) bit is a method of checking whether a Pro-
gram or Erase cycle is in progress or has complet-
ed. Figure 6 shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the word to be pro-
grammed in Flash memory to check the status.
The Data Polling (DQ7/DQ15) bit becomes the
complement of the corresponding bit of the original
data word to be programmed. The MCU continues
to poll this location, comparing data and monitor-
ing the Error Flag (DQ5/DQ13) bit. When the Data
Polling (DQ7/DQ15) bit matches the correspond-
ing bit of the original data, and the Error Flag
(DQ5/DQ13) bit remains 0, the embedded algo-
rithm is complete. If the Error Flag (DQ5/DQ13) bit
is 1, the MCU should test the Data Polling (DQ7/
DQ15) bit again since the Data Polling (DQ7/
DQ15) bit may have changed simultaneously with
the Error Flag (DQ5/DQ13) bit (see Figure 6).
The Error Flag (DQ5/DQ13) bit is set if either an in-
ternal time-out occurred while the embedded algo-
rithm attempted to program the location or if the
MCU attempted to program a 1 to a bit that was not
erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written to the Flash memory with the
word that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 6 still applies. However, the
Data Polling (DQ7/DQ15) bit is 0 until the Erase
cycle is complete. A 1 on the Error Flag (DQ5/
DQ13) bit indicates a time-out condition on the
Erase cycle, a 0 indicates no error. The MCU can
read any even location within the sector being
erased to get the Data Polling (DQ7/DQ15) bit and
the Error Flag (DQ5/DQ13) bit.
PSDsoft Express generates ANSI C code func-
tions that implement these Data Polling algo-
rithms.
Figure 6. Data Polling Flowchart
Data Toggle.
Checking the Toggle Flag (DQ6/
DQ14) bit is another method of determining wheth-
er a Program or Erase cycle is in progress or has
completed. Figure 7 shows the Data Toggle algo-
rithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location to be programmed in
Flash memory to check the status. The Toggle
Flag (DQ6/DQ14) bit toggles each time the MCU
READ DQ5 and DQ7
(DQ13 and DQ15)
at Valid Even Address
START
READ DQ7
(DQ15)
Program
or Erase
Cycle failed
Program
or Erase
Cycle is
complete
AI04920
Yes
No
Yes
No
DQ5
(DQ13)
= 1
DQ7
(D=
Data7
(Data15)
Yes
No
Issue RESET
instruction
DQ7
(D=
Data7
(Data15)
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| PSD4235G1V-12U | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G1V-12UI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235G1-C-70U | CAP 0.33UF 25V 10% TANT SMD-3216-18 TR-13-PL SN100% |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4235G2-70U | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-12UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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