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參數(shù)資料
| 型號(hào)： | PSD4235F2-20MI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 16-bit MCUs 5V Supply |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的16位微控制器5V電源 |
| 文件頁(yè)數(shù)： | 31/89頁(yè) |
| 文件大?。?/td> | 703K |
| 代理商： | PSD4235F2-20MI |
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PSD4235G2
Memory ID Registers
The 8-bit read-only Memory Status Registers are
included in the CSIOP space. The user can deter-
mine the memory configuration of the PSD device
by reading the Memory ID0 and Memory ID1 reg-
isters. The content of the registers is defined as
shown in Table 26 and Table 27.
PLDs
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using PSDsoft Express, the logic is programmed
into the device and available upon Power-up.
Table 32. DPLD and CPLD Inputs
Note: 1. The address inputs are A19-A4 in 80C51XA mode.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly discussed in the next few paragraphs,
and in more detail in the following sections. Figure
12 shows the configuration of the PLDs.
The DPLD performs address decoding for internal
components, such as memory, registers, and I/O
ports Select signals.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft
Express. An Input Bus consisting of 82 signals is
connected to the PLDs. The signals are shown in
Table 32.
The Turbo Bit in PSD.
The
PSD4235G2 can minimize power consumption by
switching to standby when inputs remain un-
changed for an extended time of about 70 ns. Re-
setting the Turbo bit to 0 (Bit 3 of the PMMR0
register) automatically places the PLDs into stand-
by if no inputs are changing. Turning the Turbo
mode off increases propagation delays while re-
ducing power consumption. See the section enti-
tled “Power Management”, on page 59, on how to
set the Turbo bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
PLDs
in
the
Input Source
Input Name
Number
of
Signals
MCU Address Bus
1
A15-A0
16
MCU Control Signals
CNTL0-CNTL2
3
Reset
RST
1
Power-down
PDN
1
Port A Input
Macrocells
PA7-PA0
8
Port B Input
Macrocells
PB7-PB0
8
Port C Input
Macrocells
PC7-PC0
8
Port D Inputs
PD3-PD0
4
Port F Inputs
PF7-PF0
8
Page Register
PGR7-PGR0
8
Macrocell A Feedback MCELLA.FB7-FB0
8
Macrocell B Feedback MCELLB.FB7-FB0
8
Flash memory
Program Status Bit
Ready/Busy
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD4235F2-20U | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F2-20UI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F2-A-12M | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F2-A-12MI | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4235F2-A-12U | Flash In-System-Programmable Peripherals for 16-Bit MCUs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4235G2-70U | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-12UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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