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參數(shù)資料
| 型號： | PSD411A1-C-70J |
| 廠商： | 意法半導體 |
| 英文描述： | High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125 |
| 中文描述： | 低成本現(xiàn)場可編程微控制器外圍設備 |
| 文件頁數(shù)： | 36/123頁 |
| 文件大?。?/td> | 657K |
| 代理商： | PSD411A1-C-70J |
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PSD4XX Famly
33
9.1.2.5 Port E Macrocell Structure
Figure 18 shows the PE Macrocell block, which consists of 8 identical macrocells. Each
macrocell output can be connected to its own I/O pin on Port E. There are 3 user
programmable global product terms output from the GPLD’s AND ARRAY which are shared
by all the macrocells in Port E:
J
PE.OE
Enable or tri-state Port PE output pins
J
PE.PR
Preset D flip flop in the macrocells
J
PE.RE
Reset/Clear D flip flop in the macrocells
Two other inputs, CLKIN and MACRO-RST, are used as clock and clear inputs to the D flip
flop. The CLKIN comes directly from the CLKIN input pin. The MACRO-RST is the same as
the Reset input pin except it is user configurable.
The circuit of a PE Macrocell is shown in Figure 19. There is only one product term from
the GPLD’s AND ARRAY as input to the macrocell. Users can select the polarity of the
output and configure the macrocell to operate as:
J
Registered Output
Select output from D flip flop
J
Combinatorial Output
Select output from OR gate
J
GPLD Input
Use Port E pin as dedicated input
J
GPLD Output
Use Port E pin as dedicated output
J
GPLD I/O
Use Port E pin as bidirectional pin
J
Macrocell Feedback
Register feedback for state machine implementations or expander feedback from the
combinatorial output, to possibly expand the number of product terms available to
another macrocell.
In case of "Buried Feedback", where the output of the macrocell is not connected
to Port E pin, Port E can be configured to perform other user defined I/O functions.
If pins PE0 and PE1 are used as bus control signal inputs (ALE, PSEN/BHE), the
corresponding macrocells' feedbacks are disabled. The bus control signals are
connected to the ZPLD Input Bus.
The two global product terms assigned for asynchronous clear (PE.RE) and preset (PE.PR)
are for proper PE Macrocell initialization.
The macrocell flip-flop can also be cleared during reset by MACRO-RST as an option. The
clock source is always the input clock CLKIN.
The PSD4XX
Architecture
(cont.)
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| PSD411A1-C-70L | High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125 |
| PSD411A1-C-70U | High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125 |
| PSD411A1-C-90JI | High Speed CMOS Logic Dual 2-to-4 Line Decoders/Demultiplexers 16-SOIC -55 to 125 |
| PSD411A1-C-90UI | High Speed CMOS Logic Hex Schmitt-Triggered Inverters 14-PDIP -55 to 125 |
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相關代理商/技術參數(shù) |
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|---|---|
| PSD411A1-C-70L | 制造商:WSI 功能描述: |
| PSD411A1-C-70U | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD411A1-C-90JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD411A1-C-90UI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD411A2 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
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