- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376249 > PSD312-15JI (意法半導體) Low Cost Field Programmable Microcontroller Peripherals PDF資料下載
參數(shù)資料
| 型號： | PSD312-15JI |
| 廠商： | 意法半導體 |
| 英文描述： | Low Cost Field Programmable Microcontroller Peripherals |
| 中文描述： | 低成本現(xiàn)場可編程微控制器外圍設備 |
| 文件頁數(shù)： | 67/85頁 |
| 文件大?。?/td> | 691K |
| 代理商： | PSD312-15JI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁當前第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
PSD3XX Famly
64
Figure 40. Port A as AD0–AD7 Timng (Track Mode) Using R/W E or R/W DS (PSD3X2/3X3)
33
25
33
32
12
28
24
34
35
DATA VALID
12
1
32
32
23
24
26
2
ADDRESS
ADDRESS
2
3
2
35
READ CYCLE
WRITE CYCLE
STABLE INPUT
STABLE INPUT
STABLE INPUT
STABLE INPUT
Direct
PAD Input
(1,4)
Multiplexed
PAD Inputs
(5,7)
A0/AD0-
A7/AD7
or AS
AS
RD/E/DS as E
WR/V
PP
or
R/W as R/W
1
3
34
27
23
RD/E/DS as DS
PA0-PA7
29
CSOi
(3,6)
ADR OUT
DATA IN
DATA
OUT
WRITTEN
DATA
ADR OUT
1. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or
R/W, transparent PC0–PC2, ALE in non-multiplexed modes.
2. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS): A0/AD0–A15/AD15,
CSI/A19 as ALE dependent A19, ALE dependent PC0–PC2.
3. CSOi = any of the chip-select output signals coming through Port B (CS0–CS7) or through Port C
(CS8–CS10).
4. CSADOUT1, which internally enables the address transfer to Port A, should be derived only from direct PAD
input signals, otherwise the address propagation delay is slowed down.
5. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively, can be
derived from any combination of direct PAD inputs and multiplexed PAD inputs.
6. The write operation signals are included in the CSOi expression.
7. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in the multiplexed
modes: A11/AD11–A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PC0–PC2.
8. CSOi product terms can include any of the PAD input signals shown in Figure 3, except for reset and CSI.
Notes for
Timng
Dagrams
相關PDF資料 |
PDF描述 |
|---|---|
| PSD312-15JM | Low Cost Field Programmable Microcontroller Peripherals |
| PSD312R-15J | Low Cost Field Programmable Microcontroller Peripherals |
| PSD312R-15JI | Low Cost Field Programmable Microcontroller Peripherals |
| PSD312R-15JM | Low Cost Field Programmable Microcontroller Peripherals |
| PSD312R-20J | Low Cost Field Programmable Microcontroller Peripherals |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD312-15JM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals |
| PSD312-15LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD312-15LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD312-15Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD312-15QI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
發(fā)布緊急采購，3分鐘左右您將得到回復。