參數(shù)資料
型號(hào): PSD312-15JI
廠(chǎng)商: 意法半導(dǎo)體
英文描述: Low Cost Field Programmable Microcontroller Peripherals
中文描述: 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備
文件頁(yè)數(shù): 30/85頁(yè)
文件大小: 691K
代理商: PSD312-15JI
PSD3XX Famly
27
14.0
System
Applications
In Figure 11, the PSD3XX is configured to interface with Intel’s 80C31, which is a 16-bit
address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order
address byte. The 80C31 uses signals RD to read from data memory and PSEN to read
from code memory. It uses WR to write into the data memory. It also uses active high reset
and ALE signals. The rest of the configuration bits, as well as the unconnected signals,
are application specific, and thus, user dependent.
MICROCONTROLLER
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
22
2
1
13
3
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD
WR
PSEN
ALE
TXD
RXD
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
A19/CSI
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
16
29
30
11
10
21
20
19
18
17
16
15
14
11
10
9
8
7
6
5
4
40
41
42
43
EA/VP
X1
X2
RESET
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
AD0/A0
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
RD
WR/V
PP
BHE/PSEN
ALE
RESET
GND
PSD3XX
80C31
34
12
V
CC
44
0.1μF
Reset
NOTE:
RESET to the PSD3XX must be the output of a RESET chip or buffer.
If RESET to the 80C31 is the output of an RC circuit, a separate buffered RC RESET to the
PSD3XX (shorter than the 80C31 RC RESET) must be provided to avoid a race condition.
Figure 11. PSD3XX Interface With Intel’s 80C31
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