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| 型號(hào)： | PSD304R |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，無(wú)的SRAM，19余個(gè)可編程輸入/輸出，通用PLD的有16個(gè)輸入） |
| 文件頁(yè)數(shù)： | 14/127頁(yè) |
| 文件大小： | 682K |
| 代理商： | PSD304R |
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PSD3XX Famly
2-14
Use This Bit
CDATA
CADDRDAT
CEDS
CA19/CSI
CALE
To
Set the data bus width to 8 or 16 bits (PSD30X only).
Set the address/data buses to multiplexed or non-multiplexed mode.
Determine the polarity and functionality of read and write. (Note 10)
Set A19/CSI to CSI (power-down) or A19 input.
Set the ALE polarity.
Set Port A either to track the low-order byte of the address/data
multiplexed bus or to select the I/O or address option.
Set the security on or off (a secured part can not be duplicated).
Set the RESET polarity.
Set PSEN and RD for combined or separate address spaces
(see Figures 9 and 10).
Configure each pin of Port A in multiplexed mode to be an I/O or
address out.
Configure each pin of Port A as an open drain or active CMOS
pull-up output.
Configure each pin of Port B as an I/O or a chip-select output.
CPAF2
CSECURITY
CRESET
COMB/SEP
CPAF1
(8 Bits)
CPACOD
(8 Bits)
CPBF
(8 Bits)
CPBCOD
(8 Bits)
CPCF
(3 Bits)
Configure each pin of Port B as an open drain or active CMOS
pull-up output.
Configure each pin of Port C as an address input or a chip-select output.
CADDHLT
Configure pins A16 – A19 to go through a latch or to have their
latch transparent.
CADLOG
(4 Bits)
Configure A16 – A19 individually as logic or address inputs. (Note 10)
CATD
Configure pins A16–A19 as PAD logic inputs or high-order address
inputs (Note 9).
Determine in non-multiplexed mode if address inputs are transparent
or latched (Note 10).
CLOT
CRRWR
Set the RD/E and WR/V
PP
or R/W pins to RD and WR pulse, or to E
strobe and R/W status (Note 9).
Configure the polarity and control methods of read and write cycles.
(Note 10)
Controls the lower-power mode.
CRRWR
CMISER
Table 4.
PSD3XX
Non-Volatile
Configuration
Bits
Configuration
Bits
The configuration bits shown in Table 4 are non-volatile cells that let the user set the device,
I/O, and control functions to the proper operational mode. Table 5 lists all configuration bits.
The configuration bits are programmed and verified during the programming phase. In
operational mode, they are not accessible. These tables are for information only since to
implement to a specific mode, the PSDsoft Development software will automatically set the
configuration bits by using simple interactive menus.
NOTES:
9. PSD3X1 only.
10. PSD302/312/303/313/304R/314R only.
This data sheet provides a complete listing of the function of each configuration bit in all
control registers. In general, you will not need to be concerned about the details of most of
these bits. The development software will set the bits automatically using information from
your design files.
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| PSD311R | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入) |
| PSD314R | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| PSD302L | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| PSD303R | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
| PSD304RL | Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD304R-12JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD304R-12LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD304R-12LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD304R-12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD304R-12UI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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