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參數(shù)資料
| 型號： | PSD303L |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有16個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，19余個可編程輸入/輸出，通用PLD的有16個輸入） |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 138K |
| 代理商： | PSD303L |
PSD3XX – Application Note 022
1-208
Simple
80C31
Design
(cont.)
Adding
Capability...
For designs that require more program and data space than the 80C31 can directly address
(128K in Separate address space and 64K in Combined space), the PSD312 and PSD313
include a paging register to expand the usable memory space. For a more complete
discussion, see WSI Application Note 015, "Using Memory Paging with the PSD3XX". This
4-bit page register enables the 80C31 to address up to 16 pages of 64K memory. To
change from one page to the next requires only that the microcontroller write the page
number of the memory page desired to the page register.
Although the page register is a good solution for systems requiring more address space
than provided by the 80C31, there are times when more memory space is desired and
using the page register may not be appropriate. Table 3 exhibits a system address map for
a Combined memory space design that requires more than 64K of memory space. We do
not want to use the page register in this case because the data memory must reside in the
same page as the program memory, such that data can be accessed by the program
without switching pages.
We can see from this memory map that the Separate mode memory model is not usable
because some EPROM addresses are in the SRAM data space. Also, the total memory
space required is 98K which exceeds the 64K memory space normally available in the
Combined mode memory model.
The solution using the PSD3XX makes use of a feature included in all PSD3XX devices.
Every PSD3XX can support up to 20 address inputs, directly enabling up to 1 meg of
address space to be accomodated. Port C pins can be configured either as chip select
outputs from the PAD or as address inputs that can be used in the memory map. Port C
pins can be configured on an individual pin basis so chip select outputs can be provided at
the same time as address inputs. By using the RD signal as an external input to the PAD via
Port C, the RD signal can be used as an extra address bit to enable up to 128KB of address
space to be accessed. See Figure 7.
When using this solution, the timing requirements are more stringent since the RD signal is
valid later than the addresses are valid. Therefore, the 80C31/PSD3XX timing that must be
satisfied is from RD valid to PSD3XX data out instead of the more usual 80C31 address
valid to PSD3XX data out. See Figure 8.
This tighter timing might require a higher speed PSD31X device. Since RD is now part of
the input address, T2 as shown above must be used as the time required for memory
access instead of T1. For example, in a 16 MHz 80C31 design, T1 is 257.5 ns (max.) and
T2 is 222.5 ns (max.). In this case, a higher speed PSD3XX is not required since a
PSD31X-20 would be fast enough to meet T1 and T2 timings.
Address
0000 – 7fff
8000 – ffff
Program Space
EPROM (32 KB)
EPROM (32 KB)
Data Space
SRAM (2 KB)
EPROM Table (32 KB)
Table 3. Combined Memory Space System Address Map
The '373 latch, I/O ports, PLD address decoder, EPROM and SRAM can be easily replaced
by a single PSD31X device, connected as shown in Figure 2. (the EPROM complement for
the PSD31X series is 32K x 8 for the PSD311, 64K x 8 for the PSD312 and 128K x 8 for the
PSD313). All are pin and function compatible.
A PSD3XX device is capable of replacing up to 6 devices in this fairly routine design. If
more complex memory maps are required, as in the system below, the system savings can
be even greater. In addition, the hardware design can be easily reused in the future since
I/O ports, chip selects, EPROM addresses and contents, etc., are all programmed into the
PSD3XX. As a result, the printed circuit board layout will not need to be changed for signifi-
cant system design changes.
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| PSD303 | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有16個輸入) |
| PSD311L | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有12個輸入) |
| PSD311 | Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有12個輸入) |
| PSD312-15IB | Field-Programmable Peripheral |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD303L-15J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD303L-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD303L-15LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD303L-15LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD303L-15U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
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