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參數(shù)資料
| 型號： | PPC440SPE-AGB533C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PowerPC 440SPe Embedded Processor |
| 中文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA675 |
| 封裝： | 27 X 27 MM, 1 MM PITCH, PLASTIC, FCBGA-675 |
| 文件頁數(shù)： | 52/80頁 |
| 文件大小： | 572K |
| 代理商： | PPC440SPE-AGB533C |
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PowerPC 440SPe Embedded Processor
52
AMCC Proprietary
Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
PCIX0Req64/PCIX0ECC6
Request 64-bit transfer or ECC6.
Normally used by the current bus master to indicate a
64-bit transfer.
Used as ECC6 for PCIX0 mode 2.
I/O
3.3V PCI or
1.5V PCI for
mode 2
4
PCIX0Reset
Sets PCI device registers and logic to a consistent state.
O
3.3V PCI
PCIX0SErr
Reports address parity errors, data parity errors on the
Special Cycle command, or other catastrophic system
errors.
I/O
3.3V PCI
4
PCIX0Stop
Indicates the current target is requesting the master to
stop the current transaction.
I/O
3.3V PCI
4
PCIX0TRDY
I
ndicates the target agent’s ability to complete the
current data phase of the transaction.
I/O
3.3V PCI
4
PCIX0VC
Voltage control output. Used to control the voltage
regulator supplying the PCI I/O voltage. See PCIX0Cap
signal.
0 = 3.3V (PCI I/O)
1 =1.5V (PCI-X DDR)
O
3.3(1.5)V PCI
PCIX0VRef0:1
Voltage reference input for PCI-X mode 2/DDR (1.5V)
I/O. Not used for PCI or PCI-X mode 1.
I
VPCIXDDR
5
DDR SDRAM Interface
BA0:2
Bank Address supporting up to 8 internal banks.
O
2.5(1.8)V
DDR SDRAM
BankSel0:3
Selects up to four external DDR SDRAM banks.
O
2.5(1.8)V
DDR SDRAM
CAS
Column Address Strobe.
O
2.5(1.8)V
DDR SDRAM
ClkEn0:3
Clock Enable. One for each external bank.
O
2.5(1.8)V
DDR SDRAM
DM0:8
Memory write data byte lane masks. MEMDM8 is the
byte lane mask for the ECC byte lane.
O
2.5(1.8)V
DDR SDRAM
DQS0:8
DQS0:8
Byte lane data strobe. DQS8 is the data strobe for the
ECC byte lane. These signals are differential pairs.
I/O
2.5(1.8)V
DDR SDRAM
DIFF
ECC0:7
ECC check bits 0:7.
I/O
2.5(1.8)V
DDR SDRAM
MemAddr14:00
Memory address bus.
Note:
MemAddr14 is the most significant bit (msb).
O
2.5(1.8)V
DDR SDRAM
MemClkOut0:5
MemClkOut0:5
Subsystem clocks. The Clock signal (differential pair) is
duplicated six times to support high loading:
Six clocks can be used for two unbuffered DIMMS.
Each individual clock signal can be enabled by
programming the SDR0_DDRCLKSET register.
O
2.5(1.8)V
DDR SDRAM
DIFF
MemData63:00
Memory data bus.
Note:
MemData63 is the most significant bit (msb).
I/O
2.5(1.8)V
DDR SDRAM
Table 6. Signal Functional Description (Sheet 3 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440SPE-AGB667C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-ANB533C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-RGB533C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-RGB667C | PowerPC 440SPe Embedded Processor |
| PPC440SPE-RNB533C | PowerPC 440SPe Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440SPE-AGB667C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
| PPC440SPE-ANB533C | 制造商:AppliedMicro 功能描述:MPU 440SPe RISC 16-Bit 0.13mm 533MHz 1.5V/3.3V 675-Pin FCBGA Tray 制造商:AMCC 功能描述:MPU 440SPE RISC 16BIT 0.13MM 533MHZ 1.5V/3.3V 675FCBGA - Trays |
| PPC440SPE-ANB667C | 制造商:AppliedMicro 功能描述:MPU 440SPe RISC 16-Bit 0.13mm 667MHz 1.5V/3.3V 675-Pin FCBGA Tray 制造商:AMCC 功能描述:MPU 440SPE RISC 16BIT 0.13MM 667MHZ 1.5V/3.3V 675FCBGA - Trays |
| PPC440SPE-ANB800C | 制造商:AppliedMicro 功能描述:MPU 440SPe RISC 16-Bit 0.13mm 800MHz 1.5V/3.3V 675-Pin FCBGA Tray 制造商:Applied Micro Circuits Corporation 功能描述:MPU 440SPe RISC 16-Bit 0.13mm 800MHz 1.5V/3.3V 675-Pin FCBGA Tray |
| PPC440SPE-RGB533C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440SPe Embedded Processor |
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