參數(shù)資料
型號： PPC440GRx-NpAfffTs
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 440GRx Embedded Processor
中文描述： 嵌入式處理器的PowerPC 440GRx
文件頁數(shù)： 59/88頁
文件大?。?/td> 603K
代理商： PPC440GRX-NPAFFFTS
440GRx – PPC440GRx Embedded Processor
Revision 1.08 – October 15, 2007
Preliminary Data Sheet
AMCC Proprietary
59
External Slave Peripheral Interface
DMAAck0:3
Used by the PPC440GRx to indicate that data transfers have
occurred.
O
3.3V LVTTL
1
DMAReq0
Used by slave peripherals to indicate they are prepared to
transfer data.
I
3.3V LVTTL
1
DMAReq1
Used by slave peripherals to indicate they are prepared to
transfer data.
I
3.3VLVTTL
1, 5
DMAReq2:3
Used by slave peripherals to indicate they are prepared to
transfer data.
I
3.3VLVTTL
1
EOT0:3/TC0:3
End Of Transfer/Terminal Count.
I/O
3.3V LVTTL
1
PerAddr02:07
Peripheral address bus used by the PPC440GRx when not in
external master mode; otherwise, used by external master.
I/O
3.3V LVTTL
1, 2
PerAddr08:31
Peripheral address bus used by the PPC440GRx when not in
external master mode; otherwise, used by external master.
I/O
3.3V LVTTL
PerData00:31
Peripheral data bus used by the PPC440GRx when not in
external master mode; otherwise, used by external master.
Note:
PerData00 is the most significant bit (msb) on this bus.
I/O
3.3V LVTTL
PerDataPar0:3
Peripheral data bus parity used by the PPC440GRx when not
in external master mode; otherwise, used by external master.
I/O
3.3V LVTTL
PerBLast
Used by either the peripheral controller, DMA controller, or
external master to indicates the last transfer of a memory
access.
I/O
3.3V LVTTL
1, 4
PerCS0
External peripheral device select.
O
3.3V LVTTL
2
PerCS1:5
External peripheral device select.
I/O
3.3V LVTTL
1, 2
PerOE
Used by either peripheral controller or DMA controller
depending upon the type of transfer involved. When the
PPC440GRx is the bus master, it enables the selected device
to drive the bus.
O
3.3V LVTTL
1, 2
PerReady
Used by a peripheral slave to indicate it is ready to transfer
data.
I
3.3V LVTTL
1
PerR/W
Used by the PPC440GRx when not in external master mode,
as output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise, it is used by the external master as an input to
indicate the direction of transfer.
I/O
3.3V LVTTL
1, 2
PerWBE0:3
External peripheral data bus byte enables.
I/O
3.3V LVTTL
1, 2
PerErr
External Error. Used as an input to record external slave
peripheral errors.
I
3.3V LVTTL
1
Table 9. Signal Functional Description (Sheet 4 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to OV
DD
(EOV
DD
for Ethernet)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to OV
DD
(EOV
DD
for Ethernet)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC440GRX-NTA400E 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays
PPC440GRX-NTA400EZ 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel
PPC440GRX-NTA533EZ 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel
PPC440GRX-NTA667EZ 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel
PPC440GRX-NUA400E 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays
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