參數(shù)資料
型號(hào)： PPC405GPR-3KB400Z
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： Power PC 405GPr Embedded Processor
中文描述： 32-BIT, 400 MHz, RISC PROCESSOR, PBGA456
封裝： 27 X 27 MM, LEAD FREE, PLASTIC, EBGA-456
文件頁(yè)數(shù)： 48/57頁(yè)
文件大?。?/td> 614K
代理商： PPC405GPR-3KB400Z
405GPr – Power PC 405GPr Embedded Processor
48
AMCC
Revision 2.04 – September 7, 2007
Data Sheet
Internal Peripheral Interface
IICSCL
IICSDA
UART0_CTS
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
UART0_RTS
UART0_Rx
UART0_Tx
UART1_RTS/
UART1_DTR
UART1_DSR/
UART1_CTS
UART1_Rx
UART1_Tx
UARTSerClk
Interrupts Interface
IRQ0:6[GPIO17:23]
JTAG Interface
TCK
TDI
TDO
TMS
TRST
System Interface
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO24
Halt
SysClk
SysErr
SysReset
TestEn
TmrClk
na
na
na
na
na
na
na
na
na
na
na
na
na
na
15.3
15.3
10.3
10.3
10.3
10.3
10.3
10.3
10.3
10.3
10.2
10.2
7.1
7.1
7.1
7.1
7.1
7.1
7.1
7.1
na
na
na
na
na
na
na
na
na
na
10.3
7.1
na
na
na
na
na
na
na
10.3
na
na
7.1
na
na
na
na
na
10.3
7.1
na
na
10.3
na
na
na
na
7.1
na
na
async
async
async
async
async
10.3
7.1
dc
dc
na
na
na
10
na
na
na
na
na
1
na
na
na
na
10.3
10.3
na
na
na
na
7.1
7.1
na
na
async
async
async
async
async
dc
dc
dc
dc
I/O Specifications—Group 1
(Sheet 2 of 3)
Notes:
1.
PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OV
DD
and I/O L is specified at 0.1OV
DD
. For all other interfaces, I/O H is specified at 2.4 V
and I/O L is specified at 0.4 V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
I/O H
(min)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I/O L
(min)
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