參數(shù)資料
型號(hào)： PPC405EP-3LB266CZ
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 405EP Embedded Processor
中文描述： 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA385
封裝： 31 X 31 MM, LEAD FREE, PLASTIC, EBGA-385
文件頁(yè)數(shù)： 36/50頁(yè)
文件大?。?/td> 373K
代理商： PPC405EP-3LB266CZ
PPC405EP – PowerPC 405EP Embedded Processor
36
AMCC
Revision 1.07 – September 10, 2007
Data Sheet
Note:
1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:
a. Case temperature, T
C
, is measured at top center of case surface with device soldered to circuit board.
b. T
A
= T
C
– P
×θ
CA
, where T
A
is ambient temperature and P is power consumption.
V
DD
Logic voltage—1.8V.
na
na
na
Other pins
Reserved
Reserved pins. Do not make voltage, ground, or signal connections to
these pins.
na
na
na
Table 7. Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only.
Operation at or beyond these maximum ratings can cause
permanent damage to the device. None of the performance specification contained in this document are guaranteed when
operating at these maximum ratings.
Characteristic
Symbol
Value
Unit
Supply Voltage (Internal Logic)
V
DD
0 to +1.95
V
Supply Voltage (I/O Interface)
OV
DD
0 to +3.6
V
PLL Supply Voltage
AV
DD
0 to +1.95
V
Input Voltage (1.8V CMOS receivers)
V
IN
0 to +1.95
V
Input Voltage (3.3V LVTTL receivers)
V
IN
0 to +3.6
V
Input Voltage (5.0V LVTTL receivers)
V
IN
0 to +5.5
V
Storage Temperature Range
T
STG
-55 to +150
°
C
Case temperature under bias
T
C
-40 to +120
°
C
Note:
All specified voltages are with respect to GND.
Table 8. Package Thermal Specifications
The PPC405EP is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the E-
PBGA packages in a convection environment are as follows:
Package—Thermal Resistance
Symbol
Airflow
ft/min (m/sec)
100 (0.51)
Unit
0 (0)
200 (1.02)
31mm, 385-balls—Junction-to-Case
θ
JC
θ
CA
2
2
2
°C/W
31mm, 385-balls—Case-to-Ambient
1
17.8
16.8
16.1
°C/W
Table 6. Signal Functional Description (Sheet 6 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Description
I/O
Type
Notes
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