
NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 24: TM3260 Debug
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
24-752
Transfer of Data to TM3260 via JTAG
Poll control register to check if input buffer is empty or not and scan in data when it is
empty and set the ifull control bit to 1 triggering an interrupt. Note that scanning in any
instruction automatically scans out the 3 least signicant bits (including the ifull or
ofull bit) of the selected TM_DBG_CTRL register.
3.2 Debug Settings
Figure 2 shows an overview of the JTAG access path from a host machine to a target
PNX15xx/952x Series system and a simplied block diagram of the PNX15xx/952x
Series processor. The JTAG Interface Module, shown separately in the diagram, may
be a PC add-on card such as PC-1149.1/100F Boundary Scan Controller Board or a
similar module connected to a PC serial or parallel port. The JTAG interface module
is necessary for PNX15xx/952x Series systems that are not plugged into a PC. For
PC-hosted PNX15xx/952x Series systems, the host based TM3260 debugger front-
end can communicate with the target resident debug monitor via the PCI bus.
Enhancements to the standard JTAG functionality include a handshake mechanism
for transferring data to and from a PNX15xx/952x Series processor’s MMIO registers,
support for posting an interrupt, and resetting processor state.
Table 3: Transfer of Data In via JTAG
Action
Number of
TCK Cycles
IR shift in SEL_IFULL_IN instruction
12
While TM_DBG_CTRL2.ifull = 1, scan in SEL_IFULL_IN instruction
11+
DR scan 33 bits of register TM_DBG_IFULL_IN
38
TOTAL
61+ cycles
Figure 2:
System with JTAG Access
Host Machine
JTAG Interface
JTAG board
Connector
Serial or Parallel
Connection
JTAG TAP (TCK, TMS, TDI, TDO)
Main
Memory
(SDRAM)
TM3260
MCU
I$
D$
JTAG
Controller
Peripherals
Scan Chain connecting possibly
other chips on board
Internal System Bus
Module
(such as a PC)
May be a PC plug-in board
CPU