
NXP Semiconductors
PNX15xx/952x Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_PNX952X_SER_N_4
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 4.0 — 03 December 2007
7-234
Registers
All IDE device registers are dened in the ATA-2 Specication. These registers can be
accessed directly from PI or indirectly via GPXIO registers. The lower ve bits of the
GPXIO address register need to be congured as follows:
Programming IDE Registers
IDE is a submodule of PCI-XIO. It shares PCI pins with other XIO blocks. Three XIO
SEL pins can be congured for use by any XIO device. Each SEL pin is associated
with the prole register in the PCI block. The prole register determines the mode of
the SEL pin, pulse width for control signals and memory apertures for each mode.
Before accessing any IDE register, the appropriate prole register needs to be
programmed. For example, if XIO_SEL[1] has been used for IDE, the sel1_prole
register needs to be programmed and IDE needs to be enabled.
At power on, the IDE disk will respond in PIO-0 mode only.
Program the appropriate register in PIO-0 mode to set PIO-4 mode.
Using sel1_prole register, set lo and high period of DIOR/DIOW pulses for PIO-4
mode.
High period in selx_prole register is used for the setup time of DA/CS lines with
DIOR/DIOW.
Low period in selx_prole register is used for the lo period of the DIOR/DIOW
pulse.
Hold of DA/CS with respect to DIOR/DIOW is always for one PCI clock.
Recommended values for sel_we_hi and sel_we_lo for PIO-0 mode are 7 and 13,
respectively (assuming a 33 MHz PCI clock).
Recommended values for sel_we_hi and sel_we_lo for PIO-4 mode are 1 and 3
respectively.
Table 4: GPXIO Address Conguration
Address to be
Written
Register Name
Address on IDE
CS1
CS0
DA2
DA1
DA0
5’b40
Data register
10000
5’b44
ERR/Feature
10001
5’b48
Sector count
10010
5’b4C
Sector number
10011
5’b50
Cylinder Low
10100
5’b54
Cylinder High
10101
5’b58
Device/Head
10110
5’b5C
Status/Command
10111
5’b38
Alternate status/Device
control
01110