參數(shù)資料
型號: PMS430E313FZ
廠商: Texas Instruments, Inc.
英文描述: MIXED SIGNAL MICROCONTROLLERS
中文描述: 混合信號微處理器
文件頁數(shù): 11/30頁
文件大?。?/td> 399K
代理商: PMS430E313FZ
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
peripherals
Peripherals connected to the CPU through a data, address, and control busses can be handled easily with
instructions for memory manipulation.
oscillator and system clock
Two clocks are used in the system: the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK
is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency. The special design of the oscillator
supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected
across two terminals without requiring any other external components.
The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It
can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK
are accessible for use by external devices at output terminal XBUF.
The controller system clock has to operate with different requirements according to the application and system
conditions. Requirements include:
High frequency in order to react quickly to system hardware requests or events
Low frequency in order to minimize current consumption, EMI, etc.
Stable frequency for timer applications e.g. real-time clock (RTC)
Enable start-stop operation with a minimum delay
These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The
compromise selected for the MSP430 uses a low-crystal frequency, which is multiplied to achieve the desired
nominal operating range:
f
(system)
= (N+1)
×
f
(crystal)
The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is
set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator
(DCO), provides immediate start-up capability together with long-term crystal stability. The frequency variation
of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1
μ
s, the maximum
possible variation is 0.33 ns. For more precise timing, the FLL can be used. This forces longer cycle times if
the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to
meet the chosen system frequency over a long period of time.
The start-up operation of the system clock depends on the previous machine state. During a power-up clear
(PUC), the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after
removal of the PUC condition. Correct operation of the FLL control logic requires the presence of a stable crystal
oscillator.
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