參數(shù)資料
型號(hào)： PM908E624ACDWBR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54
封裝： PLASTIC, SOIC-54
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 718K
代理商： PM908E624ACDWBR2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
908E624
21
If PWM control is required, the internal circuitry which drive
the internal high-side switch is an AND function between the
SPI bit HS1 (or HS2) and the PWMIN input. In order to have
HS1 on PWMIN must be high and bit HS1 must be set. The
same applies to the HS2 output.
If no PWM control is required, PWMIN must be connected to
the VDD terminal.
If overtemperature occurs on any of the three high-side
switches, the faulty switch is turned off and latched off until the
HS1 (or HS2 or HS3) bit is set to “1” in the SPI register. The
failure is reported through SPI by HSST bit.
High-Side Output HS3
This high-side switch can be used to drive small lamps, Hall-
effect sensors, or switch pull-up resistors. Control is done
through SPI. No PWM control is possible on this terminal.
Window Watchdog
The window watchdog is configurable using the external
resistor at the WDCONF terminal. The watchdog is cleared
through an SPI write operation (MODE1 and MODE2 bit). If the
WDCONF terminal is left open, a fixed watchdog period is
selected (typ. 150 ms). If no watchdog function is required, the
WDCONF terminal must be connected to GND. The watchdog
period is calculated using the following formula:
Twd [ms] = 0.991 * R [k] + 0.648
Figure 7. Window Watchdog Operation
The watchdog is cleared by an SPI write to the MODE1 and
MODE2 bits (refer to Table 2).
Table 2. Mode Selection Bits
The watchdog clear on Normal request mode (150 ms) has
no window.
SPI Interface and Register Description
The SPI is an 8-bit SPI. All bits are in a one-data byte. The
MSB (bit 7) is send first (see Figure 8). The minimum time
between two rising edges on the SSB terminal is 15
s.
Figure 8. Data Format Description
During an SPI communication, the state of MISO reports the
state of the product at time of SSB high-to-low transitions. The
status flag is latched at SSB high-to-low transitions.
The following tables describe the SPI register bit meaning,
reset value, and bit reset condition.
Table 3. SPI Register Overview
Notes
25. The first SPI read after reset returns the BATFAIL flag state on bit D4. D7 signals INT SOURCE.
W indow closed
no watch dog clear allow ed
W indow open
for w atch dog clear
W D tim ing x 50%
W D period (Tw d)
W D tim ing selected by resistor on W D C onf pin
WD timing selected by resistor on WDCONF terminal
WD period (Twd)
Window closed.
No watchdog (WD) clear allowed
Window open
for watchdog clear
MODE2
MODE1
Description
0
SLEEP mode (Note 23)
0
1
STOP mode
1
0
Normal mode + watchdog clear (Note 24)
1
Normal mode
Notes
23.
Special SPI command and sequence is implemented in order to
avoid to go into SLEEP or STOP mode with a single 8-bit SPI
command.
24.
When a zero is written to MODE1 bit while MODE2 bit is written
as a one, after the SPI command is completed MODE1 bit is set
to one and product stays in Normal mode. In order to set the
product in SLEEP mode, both MODE1 and MODE2 bits must
be written in the same 8-bit SPI command.
D7
D6
D5
D4
D3
D2
D1
D0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MOSI
MISO
D7
D6
D5
D4
D3
D2
D1
D0
W
R
LINSL2
INT
SOURCE
0
POR,
RESET
LINSL1
LINWU
or
LINFAIL
0
POR,
RESET
LIN-PU
VSOV
0
POR
HS3ON
VSUV
BATFAIL
(note 1)
0
POR,
RESET
HS2ON
VDDT
0
POR,
RESET
HS1ON
HSST
0
POR,
RESET
MODE2
L2
-
MODE1
L1
-
Write Reset
Value
Write Reset
Condition
SPI
Register
–
(Note 25)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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