參數(shù)資料
型號(hào): PM908E624ACDWBR2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54
封裝: PLASTIC, SOIC-54
文件頁(yè)數(shù): 11/24頁(yè)
文件大小: 718K
代理商: PM908E624ACDWBR2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
908E624
19
PTA5 is shared with the serial peripheral interface (SPI) but
is not accessible in the multichip approach. This terminal is
internally connected to the SPI clock of the analog die.
PTA6 is shared with the serial peripheral interface (Slave
Select) but is not accessible in the multi-die approach. This
terminal is internally connected to the SSB terminal of the
analog die. In order to get the slave select functionality, this
terminal must be used as standard output.
For details refer to the 68HC908EY16 specification.
Port B I/O Terminals
PTB7/AD7/TBCH1, PTB6/AD6/TBCH0, and PTB5/AD5–
PTB0/AD0 are special-function, bidirectional I/O port terminals
that can also be used for ADC inputs. PTB7/AD7/TBCH1 and
PTB6/AD6/TBCH0 are special function.
PTB2 and PTB0 are not accessible in the multi-die approach.
For details refer to the 68HC908EY16 specification.
Port C I/O Terminals
PTC1/MOSI and PTC0/MISO are special-function,
bidirectional I/O port terminals. PTC3/OSC2 and PTC4/OSC1
are shared with the on-chip oscillator circuit through
configuration options.
For details refer to the 68HC908EY16 specification.
Depending on the application requirements:
PTC3/OSC2 can be programmed to be OSC2.
PTC4/OSC1 can be programmed to be OSC1.
PTC2/MCLK is software selectable to be MCLK, or bus
clock out.
PTC0 and PTC1 are not directly accessible in the multi-die
approach. These terminals are internally connected to the
MISO and MOSI SPI terminals of the analog die.
Port D I/O Terminals (PTD1/TACH1, PTD0/TACH0/
BEMF)
PTD1/TACH1 and PTD0/TACH0 are special-function,
bidirectional I/O port terminals that can also be programmed to
be timer terminals.
Port E I/O Terminals (PTE1/RxD and PTE0/TxD)
PTE1/RxD and PTE0/TxD are special-function, bidirectional
I/O port terminals that can also be programmed to be enhanced
serial communication.
PTE0/TxD is internally connected to the TxD terminal of the
analog die. The connection for the receiver functionality has to
be done externally.
External Reset Terminal (RSTB)
A logic [0] on the RSTB terminal forces the MCU to a known
startup state. RSTB is bidirectional, allowing a reset of the
entire system. It is driven low when any internal reset source is
asserted. This terminal contains an internal pull-up resistor that
is always activated, even when the reset terminal is pulled low.
For details refer to the 68HC908EY16 specification.
External Interrupt Terminal (IRQB)
IRQB is an asynchronous external interrupt terminal. This
terminal contains an internal pull-up resistor that is always
activated, even when the IRQB terminal is pulled low.
Power Supply Terminals (EVDD and EVSS)
EVDD and EVSS are the power supply and ground
terminals. The MCU operates from a single power supply.
Fast signal transitions on MCU terminals place high, short-
duration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU.
For details refer to the 68HC908EY16 specification.
Analog Power Supply/Reference Terminals (VDDA,
VREFH, VSSA, and VREFL)
VDDA and VSSA are the power supply terminals for the
analog-to-digital converter (ADC).
Note VREFH is the high-reference supply for the ADC.
VDDA should be tied to the same potential as VDD via separate
traces. VREFL is the low-reference supply for the ADC. VSSA
should be tied to the same potential as VSS via separate traces.
For details refer to the 68HC908EY16 specification.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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