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19
A.C. Timing Characteristics.................................................................................................424
19.1
System Reset Timing ..............................................................................................424
19.2
OC-3 Interface Timing Characteristics....................................................................424
19.3
UTOPIA Level 3 System Interface Timing...............................................................425
S/UNI-8x155 ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
7
12.1
12.2
Master Test and Test Configuration Registers ........................................................368
JTAG Test Port ........................................................................................................371
13
Operation ............................................................................................................................380
13.1
SONET/SDH Frame Mappings and Overhead Byte Usage ...................................380
13.2
UTOPIA Level 3 ATM Cell Data Structure...............................................................384
13.3
POS-PHY Level 3 Data Structures..........................................................................385
13.4
Setting ATM Mode of Operation..............................................................................387
13.5
Setting Packet-Over-SONET/SDH Mode of Operation...........................................388
13.6
Setting SONET or SDH Mode of Operation............................................................388
13.7
Bit Error Rate Monitor .............................................................................................389
13.8
Auto Alarm Control Configuration............................................................................390
13.9
Clocking Options.....................................................................................................391
13.10
WAN Synchronization (WANS Block) .....................................................................392
13.11
Loopback Operation................................................................................................392
13.12
APS Support............................................................................................................396
13.13
JTAG Support..........................................................................................................399
13.14
Board Design Recommendations ...........................................................................403
13.15
Power Supplies .......................................................................................................404
13.16
High Speed PECL Interfaces ..................................................................................406
13.17
Clock Synthesis and Recovery ...............................................................................409
13.18
System Interface DLL Operation.............................................................................410
14
Functional Timing................................................................................................................ 411
14.1
Transmit ATM UTOPIA Level 3 System Interface ................................................... 411
14.2
Receive ATM UTOPIA Level 3 System Interface....................................................412
14.3
Transmit Packet over SONET/SDH (POS) Level 3 System Interface ....................412
14.4
Receive Packet over SONET/SDH (POS) Level 3 System Interface.....................413
14.5
Transmit Data Communication Channels ...............................................................414
14.6
Receive Data Communication Channels ................................................................415
15
Absolute Maximum Ratings................................................................................................417
16
D.C. Characterstics.............................................................................................................418
17
Power Information...............................................................................................................420
18
Microprocessor Interface Timing Characteristics................................................................421