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(above 1 MHz) should be less than value specified by the A.C. Timing section.
S/UNI-8x155 ASSP Telecom Standard Product Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
410
In general, the reference clock REFCLK is supplied by a crystal oscillator with PECL outputs.
Please refer to Table 30 for the REFCLK input jitter recommendation.
Each Clock Recovery Unit (CRU) in the S/UNI-8x155 is implemented using two digital PLL
structures. The first digital PLL (DCRU) recovers the clock from the receive data RXD+/- and
controls the jitter tolerance characteristics of the device. The second digital PLL (JAT)
attenuates the jitter on the recovered clock and controls the jitter transfer characteristics of the
device. Both PLL structures are powered from the VDDI power supply. While the digital PLLs
are robust to voltage variations, the S/UNI-8x155 must be well decoupled to prevent local
system voltage variations from affecting the jitter performance.
Please refer to the S/UNI-16x155 reference design (PMC-200-0506) for further
recommendations.
13.18 System Interface DLL Operation
The S/UNI-8x155 use digital delay lock loop (DLL) units to improve the output propagation
timing on certain digital output pins. The TFCLK and RFCLK clock inputs each have a DLL to
improve the timing on their associated interfaces.
The DLL compensates for internal timing and output pad delays by adaptively delaying the
input clock signal by approximately one clock period (1 UI) to create a new clock which
controls the internal device logic. A side effect is that the DLL units impose a minimum clock
rate on each of the clock signals.
After the S/UNI-8x155 is reset, the DLL units find the initial delay lock. This process may take
up to 3400 clock cycles to identify the lock position. During this initial lock period, device
interface timing will not meet the timing specifications listed in A.C. Timing section. The
TCA/TPA and STPA pins are held low when the TFCLK DLL is finding lock. If the clock
inputs are not stable during this period (for instance, a clock is generated using an external
PLL), the S/UNI-8x155 should be held in reset until the clocks are stable or the DLL should be
reset using software control.
The RFCLK and TFCLK DLL software resets are performed by writing 0x00 to registers
0x1036 and 0x1032 respectively. When resetting the RFCLK or TFCLK DLL units, the
associated FIFOs in the RXCP, RXFP, TXCP, TXCP, TUL3 and RUL3 blocks must also be reset
using the their FIFORST register bits. The RUN register bit is set high when the DLL finds
lock after a system or software reset.
The DLL units are sensitive to jitter on the clock inputs. The reason is that the DLL must track
the changes in clock edges cause by changes in clock frequency, temperature, voltage and jitter.
While the DLL may tolerate up to 0.4UIpp of clock jitter without losing phase lock, the output
timing may degrade with excessive input jitter. Therefore, the high frequency clock jitter