- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378055 > PM5372 (PMC-Sierra, Inc.) 40 Gbit/s Transport Switching Element PDF資料下載
參數(shù)資料
| 型號： | PM5372 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | 40 Gbit/s Transport Switching Element |
| 中文描述： | 40 Gbit / s的傳輸交換單元 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 59K |
| 代理商： | PM5372 |
PM5372
TSE
Preliminary
PMC-Sierra,Inc.
40 Gbit/s Transport Switching Element
PMC-2000328 (P1)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS
’
INTERNAL USE
Copyright PMC-Sierra, Inc. 2000
FEATURES
Implements a Time-Space-Time fabric
with STS-1/AU-3 granularity.
Provides 64 ingress STS-12 equivalent
ports for a total of 64*12 = 768 STS-1
flows.
Supports non-blocking permutation
switching of 768 STS-1 flows at STS-1
granularity.
Provides 64 egress STS-12 equivalent
ports consisting of 768 STS-1 flows.
Interfaces to STS-48 and STS-192
devices by aggregating 4 and 16 STS-
12 equivalent flows respectively.
Supports multicast and broadcast of
STS-1 streams.
Supports STS-12 equivalent flows with
an extended 8B/10B protocol over
777.6 MHz LVDS links.
Supports multi-plane (inverse
multiplexed) switch architectures in
conjunction with the PM5310 TBS
device and PM7390 S/UNI
-MACH48.
Recovers clock and data at each
ingress port, synchronizes with an
internal 77.76 MHz clock, and
produces egress streams with a
common 777.6 MHz clock.
Detects and reports inactive or erred
LVDS links via the microprocessor
interface.
Supports two sets of switch settings
and a controlled method of changing
settings on STS-1 frame boundaries.
Supports multiple fabric architectures
that range from 40 Gbit/s (1 TSE) to
160 Gbit/s (4 TSE devices) in a single
stage, and up to 2.5 Tbit/s using multi-
stage fabrics.
Ingress to egress STS-1 switching
latency of approximately 900 ns.
Supported by an efficient algorithm to
compute control settings for all
permutation loads for all supported
fabric architectures. Algorithms are
also available for multicast/broadcast
allocation.
1.8 V CMOS core and 3.3 V
CMOS/LVDS input/output.
Requires no external RAMs or logic
parts.
Provides a standard IEEE 1149.1
JTAG port.
Power Consumption of 13 W
(maximum).
Packaged in a 520 pin 40mm by 40mm
UltraBGA.
Supports a 16-bit microprocessor
interface which is used to initialize the
device, to write switch settings into on-
chip control tables, and to monitor
device performance.
JTAG
T
T
T
T
T
RN[4]
Rx 8b/10b
Frame Aligner
R8FA#3
Data
Recovery Unit
DRU #3
LVDS
Receiver
RXLV #3
Rx 8b/10b
Frame Aligner
R8FA#4
Data
Recovery Unit
DRU #4
LVDS
Receiver
RXLV #4
Rx 8b/10b
Frame Aligner
R8FA#2
Data
Recovery Unit
DRU #2
LVDS
Receiver
RXLV #2
Rx 8b/10b
Frame Aligner
R8FA#1
Data
Recovery Unit
DRU #1
LVDS
Receiver
RXLV #1
RP[4]
RN[3]
RP[3]
RN[2]
RP[2]
RN[1]
RP[1]
Egress
Time
Switch
Element
ETSE
#16
LVDS
Transmitter
TXLV #63
Serializer
PISO #63
Tx 8b/10b
Disp. Encoder
T8DE#63
LVDS
Transmitter
TXLV #64
Serializer
PISO #64
Tx 8b/10b
Disp. Encoder
T8DE#64
LVDS
Transmitter
TXLV #62
Serializer
PISO #62
Tx 8b/10b
Disp. Encoder
T8DE#62
LVDS
Transmitter
TXLV #61
Serializer
PISO #61
Tx 8b/10b
Disp. Encoder
T8DE#61
TP[61]
TN[61]
TP[62]
TN[62]
TP[63]
TN[63]
TP[64]
TN[64]
Egress
Time
Switch
Element
ETSE
#1
LVDS
Transmitter
TXLV #3
Serializer
PISO #3
Tx 8b/10b
Disp. Encoder
T8DE#3
LVDS
Transmitter
TXLV #4
Serializer
PISO #4
Tx 8b/10b
Disp. Encoder
T8DE#4
LVDS
Transmitter
TXLV #2
Serializer
PISO #2
Tx 8b/10b
Disp. Encoder
T8DE#2
LVDS
Transmitter
TXLV #1
Serializer
PISO #1
Tx 8b/10b
Disp. Encoder
T8DE#1
TP[1]
TN[1]
TP[2]
TN[2]
TP[3]
TN[3]
TP[4]
TN[4]
D
A
C
A
R
W
I
R
S
C
R
T
CSTR
Clock
Synthesizer
CSU
LVDS Transmit
Reference
TXREF
Cross-
bar
Space
Switch
Element
SSWT
Rx 8b/10b
Frame Aligner
R8FA#63
Data
Recovery Unit
DRU #63
LVDS
Receiver
RXLV #63
RN[63]
RP[63]
RN[64]
Rx 8b/10b
Frame Aligner
R8FA#64
Data
Recovery Unit
DRU #64
LVDS
Receiver
RXLV #64
RP[64]
Rx 8b/10b
Frame Aligner
R8FA#61
Data
Recovery Unit
DRU #61
LVDS
Receiver
RXLV #61
RN[61]
RP[61]
Rx 8b/10b
Frame Aligner
R8FA#62
Data
Recovery Unit
DRU #62
LVDS
Receiver
RXLV #62
RN[62]
RP[62]
Microprocessor
Interface
Ingress
Time
Switch
Element
ITSE
#16
Ingress
Time
Switch
Element
ITSE #1
BLOCK DIAGRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM5377 | Single Chip 96-Port STS-1/STM-0 Cross-Connect |
| PM5381 | SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S |
| PM5381-BI | SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S |
| PM5382 | 16-Channel OC-3c ATM and POS Physical Layer Device |
| PM5384 | Single Channel OC-3c ATM and POS Physical Layer Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM5372-BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| PM5372BIP | 制造商:PMC-Sierra 功能描述: |
| PM5372-BI-P | 制造商:PMC-Sierra 功能描述: |
| PM5376HFI | 制造商:PMC-Sierra 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。