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參數(shù)資料
| 型號： | PM5377 |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | Single Chip 96-Port STS-1/STM-0 Cross-Connect |
| 中文描述： | 單芯片96端口STS-1/STM-0交叉連接 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 36K |
| 代理商： | PM5377 |
PM5377
TSE 240
Released
Single Chip 96-Port STS-1/STM-0 Cross-Connect
PMC-2030715
Issue 2
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC.,
AND FOR ITS CUSTOMERS’ INTERNAL USE
Copyright PMC-Sierra, Inc. 2004
All rights reserved.
FEATURES
Implements a 240G memory switch
fabric with STS-1/AU-3 switching
granularity.
96 ingress and 96 egress STS-
48/STS-12 ports for a maximum of
4608 STS-1/AU-3 streams in a single
device.
Supports a single-stage, anycast
switching capacity of 240G.
SWITCH PORT CONFIGURATION
Each port can be individually
configured for 2.488Gbit/s or 622Mbit/s
operation. Ingress and egress links of
a port can be individually configured.
Optionally inserts AIS on ingress links
that are out-of-frame.
Supports unequipped overwrite, and
path AIS overwrite on a per egress port
and per egress grain basis.
Implements the ESSI Frame layer
TOH PROCESSING AND TESTING
Supports transport overhead
processing of ports in groups of 24.
TOH extract clock and data interface
capable of extracting a set of TOH
bytes per ingress port. Selection of the
bytes to be extracted is user
programmable on a per 24-port group
basis.
TOH insert clock and data interface
capable of overwriting a set of TOH
bytes per egress port. Selection of the
bytes to overwrite is user
programmable on a per 24-port group
basis.
GLOBAL FRAME
SYNCHRONIZATION
Supports frame synchronization via a
global frame pulse input signal.
Provides software readable registers
that report the difference between the
arrival time of the J0 byte and the time
the device frame reference expects to
read the J0 byte from the ingress port
FIFO on a per ingress port basis.
DELAY MANAGEMENT
Provides a 108 byte FIFO for each
ingress port to support 102 byte
maximum skew among the input links
(1312 ns for 622 Mbit/s links and 328
ns for 2.488 Gbit/s links).
Provides 13 delay management (DM)
blocks that can be allocated to a
subset of devices ports (1 through 25)
as either input delay management
(DMI) or output delay management
(DMO). Each DM block processes a
STS-48 signal for an aggregate delay
management capacity of 32.5 Gbit/s.
Supports ganging of 4 DM blocks to
form a delay management group
(DMG) capable of processing a STS-
192 signal.
Each DM block allocated as DMI
supports arbitrary frame alignment of
an STS-48 ingress signal to the frame
alignment of the synchronous
switching core.
Each DM block allocated as DMO
supports alignment of a switch core
output to a user defined frame
alignment.
Provides a software configurable delay
register to compensate for differences
in frame boundary arrival times for
ingress ports without DMI allocated.
Provides 25 software configurable
delay registers for ingress ports one
through 25 to allow arbitrary alignment
of ingress frames to the device frame
timing when DMI is allocated to an
ingress port.
ESSI Rx
DMI
R_P/N [1..25]
ESSI Tx
ESSI Tx
DMO
Microprocessor I/F
MAPS
CSU (x4)
JTAG
R_P/N [26]
ESSI Tx
R_P/N [27..96]
LBTE (x4)
T_P/N [1..25]
T_P/N [26]
T_P/N [27...96]
LB_ID[4:1][1:0]
LB_IFP[4:1]
LB_ICLK[4:1]
RJ0FP
1
M
B
T
T
T
T
T
R
N
R
I
CORE_J0FP
LBTO (x4)
LB_ED[4:1][1:0]
LB_EFP[4:1]
LB_ECLK[4:1]
RASIO
3G
Rx
ESSI Rx
ESSI Rx
Memory
Switch
Core
RASIO
3G
Rx
RASIO
3G
Rx
RASIO
3G
Tx
RASIO
3G
Tx
RASIO
3G
Tx
BLOCK DIAGRAM
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