參數(shù)資料
型號(hào)： PIC18F97J60T
廠商： Microchip Technology Inc.
英文描述： 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet
中文描述： 64/80/100-Pin，高性能，1兆位閃存微控制器與以太網(wǎng)
文件頁(yè)數(shù)： 73/474頁(yè)
文件大?。?/td> 3834K
代理商： PIC18F97J60T
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2006 Microchip Technology Inc.
Advance Information
DS39762A-page 71
PIC18F97J60 FAMILY
5.1.5
PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes to
the PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see
Section 5.1.8.1 “Computed
GOTO”
).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘
0
’. The PC increments by 2 to address
sequential instructions in the program memory.
The
CALL
,
RCALL
,
GOTO
and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.6
RETURN ADDRESS STACK
The return address stack allows any combination of up to
31 program calls and interrupts to occur. The PC is
pushed onto the stack when a
CALL
or
RCALL
instruction
is executed, or an interrupt is Acknowledged. The PC
value is pulled off the stack on a
RETURN, RETLW
or a
RETFIE
instruction (and on
ADDULNK
and
SUBULNK
instructions if the extended instruction set is enabled).
PCLATU and PCLATH are not affected by any of the
RETURN
or
CALL
instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from the stack, using these
registers.
A
CALL
type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the
CALL
). A
RETURN
type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘
00000
’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘
00000
’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
5.1.6.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is read-
able and writable. A set of three registers,
TOSU:TOSH:TOSL, holds the contents of the stack
location pointed to by the STKPTR register
(Figure 5-4). This allows users to implement a software
stack if necessary. After a
CALL, RCALL
or interrupt
(and
ADDULNK
and
SUBULNK
instructions if the
extended instruction set is enabled), the software can
read
the
pushed
value
TOSU:TOSH:TOSL registers. These values can be
placed on a user-defined software stack. At return time,
the
software
can
return
TOSU:TOSH:TOSL and do a return.
by
reading
the
these
values
to
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-4:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
00011
00010
00001
00000
001A34h
000D58h
11111
11110
11101
00010
Return Address Stack <20:0>
Top-of-Stack
TOSL
34h
TOSH
1Ah
TOSU
00h
STKPTR<4:0>
Top-of-Stack Registers
Stack Pointer
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