2003 Microchip Technology Inc.
Advance Information
DS39612A-page 301
PIC18F6X2X/8X2X
LFSR
Example:
After Instruction
FSR2H
FSR2L
MOVF
Example:
Before Instruction
REG
W
After Instruction
REG
W
Load FSR
Syntax:
Operands:
[
label
] LFSR f,k
0
≤
f
≤
2
0
≤
k
≤
4095
k
→
FSRf
None
Operation:
Status Affected:
Encoding:
1110
1111
The 12-bit literal ‘k’ is loaded into
the file select register pointed to
by ‘f’.
2
2
1110
0000
00ff
k
7
kkk
k
11
kkk
kkkk
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Write
literal ‘k’
MSB to
FSRfH
Write literal
‘k’ to FSRfL
Decode
Read literal
‘k’ MSB
Process
Data
Decode
Read literal
‘k’ LSB
Process
Data
LFSR 2, 0x3AB
=
=
0x03
0xAB
Move f
Syntax:
Operands:
[
label
] MOVF f [,d [,a]
0
≤
f
≤
255
d
∈
[0,1]
a
∈
[0,1]
f
→
dest
N, Z
Operation:
Status Affected:
Encoding:
Description:
0101
00da
ffff
ffff
The contents of register ‘f’ are
moved to a destination dependent
upon the status of ‘d’. If ‘d’ is 0, the
result is placed in W. If ‘d’ is 1, the
result is placed back in register ‘f’
(default). Location ‘f’ can be any-
where in the 256-byte bank. If ‘a(chǎn)’ is
0, the Access Bank will be
selected, overriding the BSR value.
If ‘a(chǎn)’ = 1, then the bank will be
selected as per the BSR value
(default).
1
1
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Read
register ‘f’
Q3
Q4
Decode
Process
Data
Write W
MOVF REG, 0, 0
=
=
0x22
0xFF
=
=
0x22
0x22