
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 101
PIC18F6X2X/8X2X
REGISTER 9-11:
IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0
R/W-1
U-0
R/W-1
—
CMIP
—
EEIP
bit 7
R/W-1
BCLIP
R/W-1
LVDIP
R/W-1
TMR3IP
R/W-1
CCP2IP
bit 0
bit 7
bit 6
Unimplemented:
Read as ‘0’
CMIP
: Comparator Interrupt Priority bit
1
= High priority
0
= Low priority
Unimplemented:
Read as ‘0’
EEIP
: Data EEPROM/FLASH Write Operation Interrupt Priority bit
1
= High priority
0
= Low priority
BCLIP
: Bus Collision Interrupt Priority bit
1
= High priority
0
= Low priority
LVDIP
: Low Voltage Detect Interrupt Priority bit
1
= High priority
0
= Low priority
TMR3IP
: TMR3 Overflow Interrupt Priority bit
1
= High priority
0
= Low priority
CCP2IP
: CCP2 Interrupt Priority bit
1
= High priority
0
= Low priority
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown