PIC18F97J60 FAMILY
DS39762A-page 458
Advance Information
2006 Microchip Technology Inc.
Brown-out Reset (BOR) .....................................................55
and On-Chip Voltage Regulator ...............................354
Disabling in Sleep Mode ............................................55
BSF ..................................................................................371
BSR ....................................................................................93
BTFSC .............................................................................372
BTFSS ..............................................................................372
BTG ..................................................................................373
BZ .....................................................................................374
C
C Compilers
MPLAB C18 .............................................................410
MPLAB C30 .............................................................410
Calibration (A/D Converter) ..............................................333
CALL ................................................................................374
CALLW .............................................................................403
Capture (CCP Module) .....................................................183
Associated Registers ...............................................185
CCP Pin Configuration .............................................183
CCPRxH:CCPRxL Registers ...................................183
Prescaler ..................................................................183
Software Interrupt ....................................................183
Timer1/Timer3 Mode Selection ................................183
Capture (ECCP Module) ..................................................192
Capture/Compare/PWM (CCP) ........................................181
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................182
CCPRxH Register ....................................................182
CCPRxL Register .....................................................182
Compare Mode. See Compare.
Interconnect Configurations .....................................182
Module Configuration ...............................................182
Clock Sources
Default System Clock on Reset .................................44
Oscillator Switching ....................................................42
CLRF ................................................................................375
CLRWDT ..........................................................................375
Code Examples
16 x 16 Signed Multiply Routine ..............................118
16 x 16 Unsigned Multiply Routine ..........................118
8 x 8 Signed Multiply Routine ..................................117
8 x 8 Unsigned Multiply Routine ..............................117
Changing Between Capture Prescalers ...................183
Computed GOTO Using an Offset Value ...................73
Erasing a Flash Program Memory Row ...................100
Fast Register Stack ....................................................73
How to Clear RAM (Bank 1) Using
Indirect Addressing ............................................88
Implementing a Real-Time Clock Using
a Timer1 Interrupt Service ...............................171
Initializing PORTA ....................................................136
Initializing PORTB ....................................................138
Initializing PORTC ....................................................141
Initializing PORTD ....................................................144
Initializing PORTE ....................................................148
Initializing PORTF ....................................................151
Initializing PORTG ...................................................153
Initializing PORTH ....................................................156
Initializing PORTJ ....................................................158
Loading the SSP1BUF (SSP1SR) Register .............258
Reading a Flash Program Memory Word ..................99
Saving STATUS, WREG and BSR
Registers in RAM .............................................134
Writing to Flash Program Memory ...........................102
Code Protection ............................................................... 345
COMF .............................................................................. 376
Comparator ...................................................................... 335
Analog Input Connection Considerations ................ 339
Associated Registers ............................................... 339
Configuration ........................................................... 336
Effects of a Reset .................................................... 338
Interrupts ................................................................. 338
Operation ................................................................. 337
Operation During Sleep ........................................... 338
Outputs .................................................................... 337
Reference ................................................................ 337
External Signal ................................................ 337
Internal Signal .................................................. 337
Response Time ........................................................ 337
Comparator Specifications ............................................... 426
Comparator Voltage Reference ....................................... 341
Accuracy and Error .................................................. 342
Associated Registers ............................................... 343
Configuring .............................................................. 341
Connection Considerations ...................................... 342
Effects of a Reset .................................................... 342
Operation During Sleep ........................................... 342
Compare (CCP Module) .................................................. 184
Associated Registers ............................................... 185
CCP Pin Configuration ............................................. 184
CCPRx Register ...................................................... 184
Software Interrupt .................................................... 184
Timer1/Timer3 Mode Selection ................................ 184
Compare (ECCP Module) ................................................ 192
Special Event Trigger .............................. 177, 192, 332
Computed GOTO ............................................................... 73
Configuration Bits ............................................................ 345
Configuration Register Protection .................................... 358
Context Saving During Interrupts ..................................... 134
Core Features
Easy Migration ............................................................. 7
Expanded Memory ....................................................... 7
Extended Instruction Set ............................................. 7
External Memory Bus .................................................. 7
nanoWatt Technology .................................................. 7
Oscillator Options ........................................................ 7
CPFSEQ .......................................................................... 376
CPFSGT .......................................................................... 377
CPFSLT ........................................................................... 377
Crystal Oscillator/Ceramic Resonators
(HS Modes) ................................................................ 40
Customer Change Notification Service ............................ 468
Customer Notification Service ......................................... 468
Customer Support ............................................................ 468
D
Data Addressing Modes .................................................... 88
Comparing Addressing Modes with the
Extended Instruction Set Enabled ..................... 92
Direct ......................................................................... 88
Indexed Literal Offset ................................................ 91
Indirect ....................................................................... 88
Inherent and Literal .................................................... 88