參數(shù)資料
型號(hào)： PIC18F87J60T
廠商： Microchip Technology Inc.
英文描述： 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet
中文描述： 64/80/100-Pin，高性能，1兆位閃存微控制器與以太網(wǎng)
文件頁(yè)數(shù)： 233/474頁(yè)
文件大?。?/td> 3834K
代理商： PIC18F87J60T
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2006 Microchip Technology Inc.
Advance Information
DS39762A-page 231
PIC18F97J60 FAMILY
18.4
Module Initialization
Before the Ethernet module can be used to transmit
and receive packets, certain device settings must be
initialized. Depending on the application, some config-
uration options may need to be changed. Normally,
these tasks may be accomplished once after Reset and
do not need to be changed thereafter.
18.4.1
RECEIVE BUFFER
Before receiving any packets, the receive buffer must
be initialized by setting the ERXST and ERXND Point-
ers. All memory between and including the ERXST and
ERXND addresses will be dedicated to the receive
hardware. It is recommended that the ERXST Pointers
be programmed with an even address.
Applications expecting large amounts of data and
frequent packet delivery may wish to allocate most of the
memory as the receive buffer. Applications that may
need to save older packets, or have several packets
ready for transmission, should allocate less memory.
When programming the ERXST or ERXND Pointers, the
ERXWRPT Pointer registers will automatically be
updated with the value in ERXST. The address in the
ERXWRPT will be used as the starting location when the
receive hardware begins writing received data. For track-
ing
purposes,
the ERXRDPT
additionally be programmed with the same value. To
program the ERXRDPT registers, write to ERXRDPTL
first, followed by ERXRDPTH. See
Section 18.5.3.3
“Freeing Receive Buffer Space”
for more information.
registers
should
18.4.2
TRANSMISSION BUFFER
All memory which is not used by the receive buffer is
considered to be transmission buffer. Data which is to
be transmitted should be written into any unused
space. After a packet is transmitted, however, the hard-
ware will write a 7-byte status vector into memory after
the last byte in the packet. Therefore, the application
should leave at least 7 bytes between each packet and
the beginning of the receive buffer.
18.4.3
RECEIVE FILTERS
The appropriate receive filters should be enabled or
disabled by writing to the ERXFCON register. See
Section 18.8 “Receive Filters”
for information on how
to configure it.
18.4.4
WAITING FOR THE PHY START-UP
TIMER
If the initialization procedure is being executed immedi-
ately after enabling the module (setting ECON2<5> to
‘
1
’), the PHYRDY bit should be polled to make certain
that enough time (1 ms typical) has elapsed before
proceeding to modify the PHY registers. For more
information
on
the PHY
Section 18.1.3.1 “Start-up Timer”
.
start-up timer, see
18.4.5
MAC INITIALIZATION SETTINGS
Several of the MAC registers require configuration
during initialization. This only needs to be done once
during initialization; the order of programming is
unimportant.
1.
Set the MARXEN bit (MACON1<0>) to enable
the MAC to receive frames. If using full duplex,
most applications should also set TXPAUS and
RXPAUS to allow IEEE defined flow control to
function.
Configure the PADCFG<2:0>, TXCRCEN and
FULDPX bits in the MACON3 register. Most
applications should enable automatic padding to
at least 60 bytes and always append a valid
CRC. For convenience, many applications may
wish to set the FRMLNEN bit as well to enable
frame length status reporting. The FULDPX bit
should be set if the application will be connected
to a full-duplex configured remote node;
otherwise it should be left clear.
Configure the bits in MACON4. For maintaining
compliance with IEEE 802.3, be certain to set
the DEFER bit (MACON4<6>).
Program the MAMXFL registers with the maxi-
mum frame length to be permitted to be received
or transmitted. Normal network nodes are
designed to handle packets that are 1518 bytes
or less.
Configure the Back-to-Back Inter-Packet Gap
register, MABBIPG. Most applications will
program this register with 15h when Full-Duplex
mode is used and 12h when Half-Duplex mode
is used. Refer to Register 18-19 for a more
detailed
description
inter-packet gap.
Configure the Non Back-to-Back Inter-Packet
Gap Low Byte register, MAIPGL. Most
applications will program this register with 12h.
If half duplex is used, the Non Back-to-Back
Inter-Packet Gap High Byte register, MAIPGH,
should be programmed. Most applications will
program this register to 0Ch.
If Half-Duplex mode is used, program the
Retransmission Maximum and Collision Win-
dow registers, MACLCON1 and MACLCON2.
Most applications will not need to change the
default Reset values. If the network is spread
over exceptionally long cables, the default value
of MACLCON2 may need to be increased.
Program the local MAC address into the
MAADR1:MAADR6 registers.
2.
3.
4.
5.
of
configuring
the
6.
7.
8.
9.
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PIC18F87J72-I/PT 功能描述:8位微控制器 -MCU Energy Meter 128KB LCD, CTMU, RTCC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F87J72T-I/PT 功能描述:8位微控制器 -MCU Energy Meter 128KB LCD, CTMU, RTCC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F87J90-I/PT 功能描述:8位微控制器 -MCU Segmnt LCD 128KBFlsh 4KBRAM 12MIPS RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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