2006 Microchip Technology Inc.
Advance Information
DS39762A-page 467
PIC18F97J60 FAMILY
PWM Direction Change ...........................................199
PWM Direction Change at Near 100%
Duty Cycle .......................................................199
PWM Output ............................................................186
Repeated Start Condition .........................................289
Reset, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST) and Power-up Timer (PWRT)
..........................................................................434
Send Break Character Sequence ............................318
Slave Synchronization .............................................261
Slow Rise Time (MCLR Tied to V
DD
,
V
DD
Rise > T
PWRT
) ............................................57
SPI Mode (Master Mode) .........................................260
SPI Mode (Slave Mode, CKE = 0) ...........................262
SPI Mode (Slave Mode, CKE = 1) ...........................262
Synchronous Reception (Master Mode, SREN) ......321
Synchronous Transmission ......................................319
Synchronous Transmission (Through TXEN) ..........320
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
), Case 1 .......................56
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
), Case 2 .......................57
Time-out Sequence on Power-up
(MCLR Tied to V
DD
, V
DD
Rise Tpwrt) ................56
Timer0 and Timer1 External Clock ..........................435
Transition for Entry to Idle Mode ................................50
Transition for Entry to SEC_RUN Mode ....................47
Transition for Entry to Sleep Mode ............................49
Transition for Two-Speed Start-up
(INTRC to HSPLL) ...........................................355
Transition for Wake From Idle to Run Mode ..............50
Transition for Wake From Sleep Mode (HSPLL) .......49
Transition From RC_RUN Mode to
PRI_RUN Mode .................................................48
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ..................................47
Transition to RC_RUN Mode .....................................48
Timing Diagrams and Specifications
AC Characteristics
Internal RC Accuracy .......................................430
Capture/Compare/PWM Requirements
(Including ECCP Modules) ..............................436
CLKO and I/O Requirements ...........................431, 432
EUSART Synchronous Receive
Requirements ..................................................445
EUSART Synchronous Transmission
Requirements ..................................................445
Example SPI Mode Requirements
(Master Mode, CKE = 0) ..................................437
Example SPI Mode Requirements
(Master Mode, CKE = 1) ..................................438
Example SPI Mode Requirements
(Slave Mode, CKE = 0) ....................................439
Example SPI Slave Mode
Requirements (CKE = 1) ..................................440
External Clock Requirements .................................. 429
I
2
C Bus Data Requirements
(Slave Mode) ................................................... 442
I
2
C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 441
Master SSP I
2
C Bus Data Requirements ................ 444
Master SSP I
2
C Bus Start/Stop Bits
Requirements .................................................. 443
Parallel Slave Port Requirements ............................ 436
PLL Clock ................................................................ 430
Program Memory Write Requirements .................... 433
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 434
Timer0 and Timer1 External Clock
Requirements .................................................. 435
Top-of-Stack Access .......................................................... 71
Transmitting Packets
Status Vectors ......................................................... 237
TRISE Register
PSPMODE Bit ......................................................... 160
TSTFSZ ........................................................................... 399
Two-Speed Start-up ................................................. 345, 355
Two-Word Instructions
Example Cases ......................................................... 75
TXSTAx Register
BRGH Bit ................................................................. 305
V
V
DDCORE
/V
CAP
Pin .......................................................... 354
Voltage Reference Specifications .................................... 426
Voltage Regulator (On-Chip) ........................................... 354
W
Watchdog Timer (WDT) ........................................... 345, 353
Associated Registers ............................................... 353
Control Register ....................................................... 353
Programming Considerations .................................. 353
WCOL ...................................................... 288, 289, 290, 293
WCOL Status Flag ................................... 288, 289, 290, 293
WWW Address ................................................................ 468
WWW, On-Line Support ...................................................... 6
X
XORLW ........................................................................... 399
XORWF ........................................................................... 400