
2007 Microchip Technology Inc.
Preliminary
DS39775B-page 85
PIC18F87J50 FAMILY
CCPR4H
Capture/Compare/PWM Register 4 High Byte
xxxx xxxx
63, 208
CCPR4L
Capture/Compare/PWM Register 4 Low Byte
xxxx xxxx
63, 208
CCP4CON
—
—
DC4B1
DC4B0
CCP4M3
CCP4M2
CCP4M1
CCP4M0
--00 0000
63, 208
CCPR5H
Capture/Compare/PWM Register 5 High Byte
xxxx xxxx
63, 208
CCPR5L
Capture/Compare/PWM Register 5 Low Byte
xxxx xxxx
63, 208
CCP5CON
—
—
DC5B1
DC5B0
CCP5M3
CCP5M2
CCP5M1
CCP5M0
--00 0000
63, 208
SSP2BUF
MSSP2 Receive Buffer/Transmit Register
xxxx xxxx
63, 241,
276
SSP2ADD/
SSP2MSK
(5)
MSSP2 Address Register (I
2
C Slave mode), MSSP2 Baud Rate Reload Register (I
2
C Master mode)
0000 0000
63, 241
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
0000 0000
63, 248
SSP2STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
1111 1111
63, 231,
242
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
63, 231,
243
SSP2CON2
GCEN
ACKSTAT
ACKDT
ADMSK5
(6)
ACKEN
ADMSK4
(6)
RCEN
ADMSK3
(6)
PEN
RSEN
ADMSK1
(6)
SEN
0000 0000
63, 231,
243
GCEN
ACKSTAT
ADMSK2
(6)
SEN
CMSTAT
—
—
—
—
—
—
COUT2
COUT1
---- --11
63, 337
PMADDRH/
PMDOUT1H
(8)
CS2
CS1
Parallel Master Port Address High Byte
0000 0000
64, 172
Parallel Port Out Data High Byte (Buffer 1)
0000 0000
64, 175
PMADDRL/
PMDOUT1L
(8)
Parallel Master Port Address Low Byte
0000 0000
64, 172
Parallel Port Out Data Low Byte (Buffer 0)
0000 0000
64, 172
PMDIN1H
Parallel Port In Data High Byte (Buffer 1)
0000 0000
64, 172
PMDIN1L
Parallel Port In Data Low Byte (Buffer 0)
0000 0000
64, 172
UCON
—
PPBRST
SE0
PKTDIS
USBEN
RESUME
SUSPND
—
-0x0 000-
64, 310
USTAT
—
ENDP3
ENDP2
ENDP1
ENDP0
DIR
PPBI
—
-xxx xxx-
64, 314
UEIR
BTSEF
—
—
BTOEF
DFN8EF
CRC16EF
CRC5EF
PIDEF
0--0 0000
64, 327
UIR
—
SOFIF
STALLIF
IDLEIF
TRNIF
ACTVIF
UERRIF
URSTIF
-000 0000
64, 324
UFRMH
—
—
—
—
—
FRM10
FRM9
FRM8
---- -xxx
64, 316
UFRML
FRM7
FRM6
FRM5
FRM4
FRM3
FRM2
FRM1
FRM0
xxxx xxxx
64, 316
UCFG
UTEYE
—
—
UPUEN
UTRDIS
FSEN
PPB1
PPB0
00-0 0000
64, 311
UADDR
—
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
-000 0000
64, 316
UEIE
BTSEE
—
—
BTOEE
DFN8EE
CRC16EE
CRC5EE
PIDEE
0--0 0000
64, 328
UIE
—
SOFIE
STALLIE
IDLEIE
TRNIE
ACTVIE
UERRIE
URSTIE
-000 0000
64, 326
UEP15
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
64, 315
UEP14
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
64, 315
UEP13
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
64, 315
UEP12
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
64, 315
UEP11
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
64, 315
UEP10
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
64, 315
UEP9
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
64, 315
UEP8
—
—
—
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL
---0 0000
64, 315
TABLE 5-5:
REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
Legend:
Note
x
= unknown,
u
= unchanged,
-
= unimplemented,
q
= value depends on condition.
Bold
indicates shared-access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address, available when WDTCON<4> =
0
.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> =
1
.
Reset value is ‘
0
’ when Two-Speed Start-up is enabled and ‘
1
’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> =
1001
.
Alternate names and definitions for these bits when the MSSP module is operating in I
2
C Slave mode. See
Section 19.4.3.2 “Address
Masking Modes”
for details
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘
0
’. Reset values are
shown for 80-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See
Section 11.1.2 “Data Registers”
for more information.
1:
2:
3:
4:
5:
6:
7:
8: