
PIC18F87J50 FAMILY
DS39775B-page 386
Preliminary
2007 Microchip Technology Inc.
Example:
Example:
IORLW
Inclusive OR Literal with W
Syntax:
IORLW k
Operands:
0
≤
k
≤
255
Operation:
(W) .OR. k
→
W
Status Affected:
N, Z
Encoding:
0000
1001
kkkk
kkkk
Description:
The contents of W are ORed with the
eight-bit literal ‘k’. The result is placed
in W.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to
W
IORLW
35h
Before Instruction
W
After Instruction
W
=
9Ah
=
BFh
IORWF
Inclusive OR W with f
Syntax:
IORWF f {,d {,a}}
Operands:
0
≤
f
≤
255
d
∈
[0,1]
a
∈
[0,1]
Operation:
(W) .OR. (f)
→
dest
Status Affected:
N, Z
Encoding:
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If ‘d’ is
‘
0
’, the result is placed in W. If ‘d’ is ‘
1
’,
the result is placed back in register ‘f’
(default).
If ‘a(chǎn)’ is ‘
0
’, the Access Bank is selected.
If ‘a(chǎn)’ is ‘
1
’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘
0
’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
≤
95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
IORWF RESULT, 0, 1
Before Instruction
RESULT =
W
After Instruction
RESULT =
W
13h
91h
=
13h
93h
=