2007 Microchip Technology Inc.
Preliminary
DS39775B-page 473
PIC18F87J50 FAMILY
I
2
C Bus Start/Stop Bits Requirements
(Slave Mode) ...................................................449
MSSPx I
2
C Bus Data Requirements ........................452
MSSPx I
2
C Bus Start/Stop Bits Requirements ........451
Parallel Master Port Read Requirements ................443
Parallel Master Port Write Requirements .................444
PLL Clock .................................................................436
Program Memory Read Requirements ....................438
Program Memory Write Requirements ....................439
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................440
Timer0 and Timer1 External Clock
Requirements ..................................................441
USB Full-Speed Requirements ................................456
USB Low-Speed Requirements ...............................456
TSTFSZ ...........................................................................403
Two-Speed Start-up .................................................347, 359
Two-Word Instructions
Example Cases ..........................................................75
TXSTAx Register
BRGH Bit .................................................................281
U
Universal Serial Bus
Address Register (UADDR) .....................................316
Associated Registers ...............................................332
Buffer Descriptor Table ............................................317
Buffer Descriptors ....................................................317
Address Validation ...........................................320
Assignment in Different Buffering Modes ........322
BDnSTAT Register (CPU Mode) .....................318
BDnSTAT Register (SIE Mode) .......................320
Byte Count .......................................................320
Example ...........................................................317
Memory Map ....................................................321
Ownership ........................................................317
Ping-Pong Buffering .........................................321
Register Summary ...........................................322
Status and Configuration .................................317
Class Specifications and Drivers .............................334
Descriptors ...............................................................334
Endpoint Control ......................................................315
Enumeration .............................................................334
External Pull-up Resistors ........................................313
Eye Pattern Test Enable ..........................................313
Firmware and Drivers ...............................................332
Frame Number Registers ........................................ 316
Frames .................................................................... 333
Internal Pull-up Resistors ........................................ 313
Internal Transceiver ................................................. 311
Interrupts ................................................................. 323
and USB Transactions ..................................... 323
Layered Framework ................................................. 333
Oscillator Requirements .......................................... 332
Overview .......................................................... 309, 333
Ping-Pong Buffer Configuration ............................... 313
Power ...................................................................... 333
Power Modes ........................................................... 329
Bus Power Only ............................................... 329
Dual Power with Self-Power Dominance ......... 330
Self-Power Only ............................................... 329
RAM ......................................................................... 316
Memory Map .................................................... 316
Speed ...................................................................... 334
Status and Control ................................................... 310
Transfer Types ........................................................ 333
UFRMH:UFRML Registers ...................................... 316
USB RAM
Serial Interface Engine (SIE) ..................................... 76
USB Specifications .......................................................... 432
USB.
See
Universal Serial Bus.
V
V
DDCORE
/V
CAP
Pin .......................................................... 358
Voltage Reference Specifications .................................... 431
Voltage Regulator (On-Chip) ........................................... 358
Operation in Sleep Mode ......................................... 359
W
Watchdog Timer (WDT) ........................................... 347, 356
Associated Registers ............................................... 357
Control Register ....................................................... 356
During Oscillator Failure .......................................... 360
Programming Considerations .................................. 356
WCOL ...................................................... 265, 266, 267, 270
WCOL Status Flag ................................... 265, 266, 267, 270
WWW Address ................................................................ 474
WWW, On-Line Support ...................................................... 5
X
XORLW ........................................................................... 403
XORWF ........................................................................... 404