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PIC18F87J50 FAMILY
DS39775B-page 470
Preliminary
2007 Microchip Technology Inc.
Output Relationships (Active-Low) ...........................221
Period .......................................................................219
Programmable Dead-Band Delay ............................226
Setup for PWM Operation ........................................229
Start-up Considerations ...........................................227
Q
Q Clock ....................................................................213, 220
R
RAM.
See
Data Memory.
RC_IDLE Mode ..................................................................51
RC_RUN Mode ..................................................................48
RCALL ..............................................................................393
RCON Register
Bit Status During Initialization ....................................58
Reader Response ............................................................475
Register File .......................................................................78
Register File Summary .................................................81–86
Registers
ADCON0 (A/D Control 0) .........................................299
ADCON1 (A/D Control 1) .........................................300
ANCON0 (A/D Port Configuration 2) ........................301
ANCON1 (A/D Port Configuration 1) ........................301
BAUDCONx (Baud Rate Control) ............................280
BDnSTAT (Buffer Descriptor n Status,
CPU Mode) ......................................................319
BDnSTAT (Buffer Descriptor n Status,
SIE Mode) ........................................................320
CCPxCON (CCPx Control) ......................................207
CCPxCON (ECCPx Control) ....................................215
CMSTAT (Comparator Status) .................................337
CMxCON (Comparator Control x) ............................336
CONFIG1H (Configuration 1 High) ..........................350
CONFIG1L (Configuration 1 Low) ............................349
CONFIG2H (Configuration 2 High) ..........................352
CONFIG3H (Configuration 3 High) ..........................354
CONFIG3L (Configuration 3 Low) ......................69, 353
CVRCON (Comparator Voltage
Reference Control) ...........................................344
DEVID1 (Device ID 1) ..............................................355
DEVID2 (Device ID 2) ..............................................355
ECCPxAS (ECCPx Auto-Shutdown Control) ...........227
ECCPxDEL (ECCPx PWM Delay) ...........................226
EECON1 (EEPROM Control 1) ..................................97
INTCON (Interrupt Control) ......................................121
INTCON2 (Interrupt Control 2) .................................122
INTCON3 (Interrupt Control 3) .................................123
IPR1 (Peripheral Interrupt Priority 1) ........................130
IPR2 (Peripheral Interrupt Priority 2) ........................131
IPR3 (Peripheral Interrupt Priority 3) ........................132
MEMCON (External Memory Bus Control) ..............106
ODCON1 (Peripheral Open-Drain Control 1) ...........137
ODCON2 (Peripheral Open-Drain Control 2) ...........137
ODCON3 (Peripheral Open-Drain Control 3) ...........137
OSCCON (Oscillator Control) ....................................42
OSCTUNE (Oscillator Tuning) ...................................38
PADCFG1 (Pad Configuration Control 1) ................138
PIE1 (Peripheral Interrupt Enable 1) ........................127
PIE2 (Peripheral Interrupt Enable 2) ........................128
PIE3 (Peripheral Interrupt Enable 3) ........................129
PIR1 (Peripheral Interrupt Request (Flag) 1) ...........124
PIR2 (Peripheral Interrupt Request (Flag) 2) ...........125
PIR3 (Peripheral Interrupt Request (Flag) 3) ...........126
PMADDRH (Parallel Port Address High Byte) .........172
PMCONH (Parallel Port Control High Byte) .............166
PMCONL (Parallel Port Control Low Byte) .............. 167
PMEH (Parallel Port Enable High Byte) ................... 169
PMEL (Parallel Port Enable Low Byte) .................... 170
PMMODEH (Parallel Port Mode High Byte) ............ 168
PMMODEL (Parallel Port Mode Low Byte) .............. 169
PMSTATH (Parallel Port Status High Byte) ............. 170
PMSTATL (Parallel Port Status Low Byte) .............. 171
RCON (Reset Control) ....................................... 54, 133
RCSTAx (Receive Status and Control) .................... 279
SSPxCON1 (MSSPx Control 1, I
2
C Mode) .............. 243
SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 233
SSPxMSK (I
2
C Slave Address Mask) ...................... 245
SSPxSTAT (MSSPx Status, I
2
C Mode) ................... 242
SSPxSTAT (MSSPx Status, SPI Mode) .................. 232
STATUS .................................................................... 87
STKPTR (Stack Pointer) ............................................ 72
T0CON (Timer0 Control) ......................................... 189
T1CON (Timer1 Control) ......................................... 193
T2CON (Timer2 Control) ......................................... 199
T3CON (Timer3 Control) ......................................... 201
T4CON (Timer4 Control) ......................................... 205
TXSTAx (Transmit Status and Control) ................... 278
UCFG (USB Configuration) ..................................... 312
UCON (USB Control) ............................................... 310
UEIE (USB Error Interrupt Enable) .......................... 328
UEIR (USB Error Interrupt Status) ........................... 327
UEPn (USB Endpoint n Control) .............................. 315
UIE (USB Interrupt Enable) ..................................... 326
UIR (USB Interrupt Status) ...................................... 324
USTAT (USB Status) ............................................... 314
WDTCON (Watchdog Timer Control) ...................... 357
RESET ............................................................................. 393
Reset ................................................................................. 53
Brown-out Reset (BOR) ............................................. 53
MCLR Reset, During Power-Managed Modes .......... 53
MCLR Reset, Normal Operation ................................ 53
Power-on Reset (POR) .............................................. 53
RESET Instruction ..................................................... 53
Stack Full Reset ......................................................... 53
Stack Underflow Reset .............................................. 53
Watchdog Timer (WDT) Reset .................................. 53
Resets .............................................................................. 347
Brown-out Reset (BOR) ........................................... 347
Oscillator Start-up Timer (OST) ............................... 347
Power-on Reset (POR) ............................................ 347
Power-up Timer (PWRT) ......................................... 347
RETFIE ............................................................................ 394
RETLW ............................................................................ 394
RETURN .......................................................................... 395
Revision History ............................................................... 461
RLCF ............................................................................... 395
RLNCF ............................................................................. 396
RRCF ............................................................................... 396
RRNCF ............................................................................ 397
S
SCKx ................................................................................ 231
SDIx ................................................................................. 231
SDOx ............................................................................... 231
SEC_IDLE Mode ............................................................... 50
SEC_RUN Mode ................................................................ 46
Serial Clock, SCKx .......................................................... 231
Serial Data In (SDIx) ........................................................ 231
Serial Data Out (SDOx) ................................................... 231
Serial Peripheral Interface.
See
SPI Mode.
SETF ................................................................................ 397