
PIC18F87J50 FAMILY
DS39775B-page 384
Preliminary
2007 Microchip Technology Inc.
GOTO
Example:
Example:
Unconditional Branch
Syntax:
GOTO k
Operands:
0
≤
k
≤
1048575
Operation:
k
→
PC<20:1>
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
1111
k
19
kkk
k
7
kkk
kkkk
kkkk
0
kkkk
8
Description:
GOTO
allows an unconditional branch
anywhere within entire 2-Mbyte memory
range. The 20-bit value ‘k’ is loaded into
PC<20:1>.
GOTO
is always a two-cycle
instruction.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
No
Q4
Decode
Read literal
‘k’<7:0>,
operation
Read literal
‘k’<19:8>,
Write to PC
No
operation
No
operation
No
operation
No
operation
GOTO THERE
After Instruction
PC =
Address
(THERE)
INCF
Increment f
Syntax:
INCF f {,d {,a}}
Operands:
0
≤
f
≤
255
d
∈
[0,1]
a
∈
[0,1]
Operation:
(f) +
1
→
dest
Status Affected:
C, DC, N, OV, Z
Encoding:
0010
10da
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘
0
’, the result is
placed in W. If ‘d’ is ‘
1
’, the result is
placed back in register ‘f’ (default).
If ‘a(chǎn)’ is ‘
0
’, the Access Bank is selected.
If ‘a(chǎn)’ is ‘
1
’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘
0
’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
≤
95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
INCF
CNT, 1, 0
Before Instruction
CNT
Z
C
DC
After Instruction
CNT
Z
C
DC
=
=
=
=
FFh
0
=
=
=
=
00h
1
1
1